The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Os switches ATM multibuffer compartilhados são atraentes porque podem estender a largura de banda da memória pelo uso de múltiplas memórias buffer independentes. Embora a acessibilidade paralela permita uma melhoria considerável na largura de banda da memória, é necessária uma atribuição adequada de endereços de memória às células para melhor utilizar a largura de banda potencial. Neste artigo, apresentamos uma estratégia eficiente de posicionamento de células para switches ATM multibuffer compartilhados. É baseado em uma combinação de dois conceitos-chave: distribuição uniforme para gravações e localidade de referência para leituras. O primeiro é reduzir a taxa de perda de células devido a conflitos de estouro e acesso de gravação. A última é ter células destinadas à mesma porta de saída lidas na mesma memória buffer para minimizar conflitos de acesso de leitura. Um único limite é empregado para atribuir localizações de memória de forma adaptativa, dependendo da distribuição de células entre as memórias buffer compartilhadas. A estratégia proposta demonstra superar as existentes, em termos de taxa de perda de células, atraso de célula e rendimento. Além disso, os ganhos de desempenho foram obtidos com um circuito de controle simples.
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Pong-Gyou LEE, Woon-Cheon KANG, Yoon-Hwa CHOI, "An Efficient Cell Placement Strategy for Shared Multibuffer ATM Switches" in IEICE TRANSACTIONS on Communications,
vol. E82-B, no. 9, pp. 1424-1431, September 1999, doi: .
Abstract: Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient cell placement strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write-access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read-access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e82-b_9_1424/_p
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@ARTICLE{e82-b_9_1424,
author={Pong-Gyou LEE, Woon-Cheon KANG, Yoon-Hwa CHOI, },
journal={IEICE TRANSACTIONS on Communications},
title={An Efficient Cell Placement Strategy for Shared Multibuffer ATM Switches},
year={1999},
volume={E82-B},
number={9},
pages={1424-1431},
abstract={Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient cell placement strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write-access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read-access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - An Efficient Cell Placement Strategy for Shared Multibuffer ATM Switches
T2 - IEICE TRANSACTIONS on Communications
SP - 1424
EP - 1431
AU - Pong-Gyou LEE
AU - Woon-Cheon KANG
AU - Yoon-Hwa CHOI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E82-B
IS - 9
JA - IEICE TRANSACTIONS on Communications
Y1 - September 1999
AB - Shared multibuffer ATM switches are attractive since they can extend memory bandwidth by the use of multiple independent buffer memories. Although the parallel accessibility allows a considerable improvement in memory bandwidth, a proper assignment of memory addresses to cells is necessary to better utilize the potential bandwidth. In this paper, we present an efficient cell placement strategy for shared multibuffer ATM switches. It is based on a combination of two key concepts, uniform distribution for writes and reference locality for reads. The former is to reduce cell loss ratio due to overflow and write-access conflicts. The latter is to have cells destined for the same output port read from the same buffer memory to minimize read-access conflicts. A single threshold is employed to assign memory locations adaptively depending on the cell distribution among the shared buffer memories. The proposed strategy is shown to outperform the existing ones, in terms of cell loss ratio, cell delay, and throughput. Moreover, the performance gains have been made with a simple control circuit.
ER -