The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Esta carta mostra os resultados de uma série de simulações em nível de link conduzidas para avaliar o desempenho de equalizadores espaciais e temporais (equalizadores S/T) usando dados de medição de campo. A configuração do equalizador espacial e temporal discutido nesta carta pode ser expressa como uma cascata de uma antena de matriz adaptativa e um estimador de sequência de máxima verossimilhança (MLSE): cada um dos elementos da antena da matriz adaptativa tem uma linha de atraso com derivação fracionadamente espaçada (FTDL), e o MLSE possui taps cobrindo uma parte do perfil de atraso do canal. O desempenho da taxa de erro de bit (BER) dos equalizadores S/T é apresentado e a sensibilidade do desempenho ao deslocamento do tempo do símbolo é investigada.
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Takefumi YAMADA, Shigeru TOMISATO, Tadashi MATSUMOTO, Uwe TRAUTWEIN, "Results of Link-Level Simulations Using Field Measurement Data for an FTDL-Spatial/ MLSE-Temporal Equalizer" in IEICE TRANSACTIONS on Communications,
vol. E84-B, no. 7, pp. 1956-1960, July 2001, doi: .
Abstract: This letter shows the results of a series of link level simulations conducted to evaluate the performances of spatial and temporal equalizers (S/T-equalizers) using field measurement data. The configuration of the spatial and temporal equalizer discussed in this letter can be expressed as a cascade of an adaptive array antenna and maximum likelihood sequence estimator (MLSE): each of the adaptive array antenna elements has a fractionally spaced tapped delay line (FTDL), and the MLSE has taps covering a portion of channel delay profile. Bit error rate (BER) performances of the S/T-equalizers are presented, and performance sensitivity to symbol timing offset is investigated.
URL: https://global.ieice.org/en_transactions/communications/10.1587/e84-b_7_1956/_p
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@ARTICLE{e84-b_7_1956,
author={Takefumi YAMADA, Shigeru TOMISATO, Tadashi MATSUMOTO, Uwe TRAUTWEIN, },
journal={IEICE TRANSACTIONS on Communications},
title={Results of Link-Level Simulations Using Field Measurement Data for an FTDL-Spatial/ MLSE-Temporal Equalizer},
year={2001},
volume={E84-B},
number={7},
pages={1956-1960},
abstract={This letter shows the results of a series of link level simulations conducted to evaluate the performances of spatial and temporal equalizers (S/T-equalizers) using field measurement data. The configuration of the spatial and temporal equalizer discussed in this letter can be expressed as a cascade of an adaptive array antenna and maximum likelihood sequence estimator (MLSE): each of the adaptive array antenna elements has a fractionally spaced tapped delay line (FTDL), and the MLSE has taps covering a portion of channel delay profile. Bit error rate (BER) performances of the S/T-equalizers are presented, and performance sensitivity to symbol timing offset is investigated.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Results of Link-Level Simulations Using Field Measurement Data for an FTDL-Spatial/ MLSE-Temporal Equalizer
T2 - IEICE TRANSACTIONS on Communications
SP - 1956
EP - 1960
AU - Takefumi YAMADA
AU - Shigeru TOMISATO
AU - Tadashi MATSUMOTO
AU - Uwe TRAUTWEIN
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Communications
SN -
VL - E84-B
IS - 7
JA - IEICE TRANSACTIONS on Communications
Y1 - July 2001
AB - This letter shows the results of a series of link level simulations conducted to evaluate the performances of spatial and temporal equalizers (S/T-equalizers) using field measurement data. The configuration of the spatial and temporal equalizer discussed in this letter can be expressed as a cascade of an adaptive array antenna and maximum likelihood sequence estimator (MLSE): each of the adaptive array antenna elements has a fractionally spaced tapped delay line (FTDL), and the MLSE has taps covering a portion of channel delay profile. Bit error rate (BER) performances of the S/T-equalizers are presented, and performance sensitivity to symbol timing offset is investigated.
ER -