The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Os switches baseados em FPGA são atraentes hoje em dia devido ao equilíbrio entre desempenho de hardware e flexibilidade de software. O analisador de pacotes, como componente fundamental dos switches baseados em FPGA, serve para identificar e extrair campos específicos usados nas decisões de encaminhamento, por exemplo, endereço IP de destino. No entanto, os analisadores tradicionais são demasiado rígidos para acomodar novos protocolos. Além disso, os FPGAs costumam ter uma frequência de clock muito menor e menos recursos de hardware, em comparação com os ASICs. Neste artigo, apresentamos PLANET, uma arquitetura programável de análise paralela em nível de pacote para switches baseados em FPGA, para superar essas duas limitações. Primeiro, o PLANET possui programação flexível para atualizar algoritmos de análise em tempo de execução. Em segundo lugar, o PLANET explora altamente o paralelismo dentro da análise de pacotes para compensar a baixa frequência de clock do FPGA e reduzir o consumo de recursos com o design de reciclagem de um bloco. Implementamos o PLANET em um protótipo de switch baseado em FPGA com protocolos de datacenter bem integrados. Os resultados da avaliação mostram que nosso projeto pode analisar pacotes em até 100 Gbps, bem como manter uma latência de análise relativamente baixa e menos recursos de hardware do que as propostas existentes.
Junnan LI
National University of Defense Technology
Biao HAN
National University of Defense Technology
Zhigang SUN
National University of Defense Technology
Tao LI
National University of Defense Technology
Xiaoyan WANG
Ibaraki University
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Junnan LI, Biao HAN, Zhigang SUN, Tao LI, Xiaoyan WANG, "Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches" in IEICE TRANSACTIONS on Communications,
vol. E102-B, no. 9, pp. 1862-1874, September 2019, doi: 10.1587/transcom.2018EBP3333.
Abstract: FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.2018EBP3333/_p
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@ARTICLE{e102-b_9_1862,
author={Junnan LI, Biao HAN, Zhigang SUN, Tao LI, Xiaoyan WANG, },
journal={IEICE TRANSACTIONS on Communications},
title={Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches},
year={2019},
volume={E102-B},
number={9},
pages={1862-1874},
abstract={FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.},
keywords={},
doi={10.1587/transcom.2018EBP3333},
ISSN={1745-1345},
month={September},}
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TY - JOUR
TI - Exploiting Packet-Level Parallelism of Packet Parsing for FPGA-Based Switches
T2 - IEICE TRANSACTIONS on Communications
SP - 1862
EP - 1874
AU - Junnan LI
AU - Biao HAN
AU - Zhigang SUN
AU - Tao LI
AU - Xiaoyan WANG
PY - 2019
DO - 10.1587/transcom.2018EBP3333
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E102-B
IS - 9
JA - IEICE TRANSACTIONS on Communications
Y1 - September 2019
AB - FPGA-based switches are appealing nowadays due to the balance between hardware performance and software flexibility. Packet parser, as the foundational component of FPGA-based switches, is to identify and extract specific fields used in forwarding decisions, e.g., destination IP address. However, traditional parsers are too rigid to accommodate new protocols. In addition, FPGAs usually have a much lower clock frequency and fewer hardware resources, compared to ASICs. In this paper, we present PLANET, a programmable packet-level parallel parsing architecture for FPGA-based switches, to overcome these two limitations. First, PLANET has flexible programmability of updating parsing algorithms at run-time. Second, PLANET highly exploits parallelism inside packet parsing to compensate FPGA's low clock frequency and reduces resource consumption with one-block recycling design. We implemented PLANET on an FPGA-based switch prototype with well-integrated datacenter protocols. Evaluation results show that our design can parse packets at up to 100 Gbps, as well as maintain a relative low parsing latency and fewer hardware resources than existing proposals.
ER -