The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Com a crescente demanda por aplicações multimídia de alto desempenho em canais sem fio, precisamos desenvolver um sistema de Controle de Acesso Médio (MAC) que suporte alto rendimento e melhorias na qualidade do serviço. Este artigo apresenta a análise padrão, arquitetura de projeto e questões de projeto que levam à implementação de um sistema MAC baseado em IEEE 802.11e que suporta throughput MAC de mais de 100 Mbps. Para atender às restrições de tempo da camada MAC, é adotada uma abordagem de co-design de hardware/software. A arquitetura MAC proposta é implementada no protótipo Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) e conectada a um computador host através de uma interface externa Universal Serial Bus (USB). A utilização total de recursos do FPGA é de 11,508 de 33,088 (34%) fatias disponíveis. A taxa de transferência MAC medida é de 100.7 Mbps e 109.2 Mbps para categorias de acesso de voz e vídeo, transmitida a uma taxa de dados de 260 Mbps com base na camada física IEEE 802.11n (PHY), usando o mecanismo de acesso de canal de função de coordenação híbrida baseado em contenção.
IEEE802.11e, MAC, EDCA, FPGA
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Min Li HUANG, Jin LEE, Hendra SETIAWAN, Hiroshi OCHI, Sin-Chong PARK, "A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard" in IEICE TRANSACTIONS on Communications,
vol. E93-B, no. 4, pp. 948-960, April 2010, doi: 10.1587/transcom.E93.B.948.
Abstract: With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.
URL: https://global.ieice.org/en_transactions/communications/10.1587/transcom.E93.B.948/_p
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@ARTICLE{e93-b_4_948,
author={Min Li HUANG, Jin LEE, Hendra SETIAWAN, Hiroshi OCHI, Sin-Chong PARK, },
journal={IEICE TRANSACTIONS on Communications},
title={A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard},
year={2010},
volume={E93-B},
number={4},
pages={948-960},
abstract={With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.},
keywords={},
doi={10.1587/transcom.E93.B.948},
ISSN={1745-1345},
month={April},}
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TY - JOUR
TI - A High Throughput Medium Access Control Implementation Based on IEEE 802.11e Standard
T2 - IEICE TRANSACTIONS on Communications
SP - 948
EP - 960
AU - Min Li HUANG
AU - Jin LEE
AU - Hendra SETIAWAN
AU - Hiroshi OCHI
AU - Sin-Chong PARK
PY - 2010
DO - 10.1587/transcom.E93.B.948
JO - IEICE TRANSACTIONS on Communications
SN - 1745-1345
VL - E93-B
IS - 4
JA - IEICE TRANSACTIONS on Communications
Y1 - April 2010
AB - With the growing demand for high-performance multimedia applications over wireless channels, we need to develop a Medium Access Control (MAC) system that supports high throughput and quality of service enhancements. This paper presents the standard analysis, design architecture and design issues leading to the implementation of an IEEE 802.11e based MAC system that supports MAC throughput of over 100 Mbps. In order to meet the MAC layer timing constraints, a hardware/software co-design approach is adopted. The proposed MAC architecture is implemented on the Xilinx Virtex-II Pro Field-Programmable Gate Array (FPGA) (XC2VP70-5FF1704C) prototype, and connected to a host computer through an external Universal Serial Bus (USB) interface. The total FPGA resource utilization is 11,508 out of 33,088 (34%) available slices. The measured MAC throughput is 100.7 Mbps and 109.2 Mbps for voice and video access categories, transmitted at a data rate of 260 Mbps based on IEEE 802.11n Physical Layer (PHY), using the contention-based hybrid coordination function channel access mechanism.
ER -