The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Esta carta emprega a teoria da linha de transmissão para os circuitos de correspondência de impedância para um amplificador de potência (PA) de chip único e verifica aplicações de LAN sem fio de banda de 5 GHz (IEEE 802.11a). Os circuitos correspondentes apresentados são compostos por ressonadores de linha meandro de guia de onda coplanar apoiado por condutor (CPW) e impedância (K) inversores. Uma das vantagens dos circuitos apresentados é que ele pode economizar espaço no chip ocupado pelos circuitos correspondentes em comparação com os indutores espirais, reduzindo assim o custo. O chip protótipo, que consiste em PA e circuitos correspondentes, é projetado empregando a teoria apresentada e fabricado. Alguns dos resultados medidos para verificar a teoria do design são apresentados.
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Ramesh Kumar POKHAREL, Haruichi KANAYA, Keiji YOSHIDA, "Design of 5 GHz-Band Power Amplifier with On-Chip Matching Circuits Using CPW Impedance (K) Inverters" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 11, pp. 1824-1827, November 2008, doi: 10.1093/ietele/e91-c.11.1824.
Abstract: This Letter employs transmission-line theory for the impedance-matching circuits for a single-chip power amplifier (PA) and verifies for 5 GHz-band wireless LAN (IEEE 802.11a) applications. The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverters. One of the advantages of the presented circuits is that it can save on-chip space occupied by the matching circuits compared to that using the spiral inductors, thus reducing the cost. The prototype chip, which consists of PA and matching circuits, is designed employing the presented theory and fabricated. A few of the measured results to verify the design theory are presented.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.11.1824/_p
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@ARTICLE{e91-c_11_1824,
author={Ramesh Kumar POKHAREL, Haruichi KANAYA, Keiji YOSHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of 5 GHz-Band Power Amplifier with On-Chip Matching Circuits Using CPW Impedance (K) Inverters},
year={2008},
volume={E91-C},
number={11},
pages={1824-1827},
abstract={This Letter employs transmission-line theory for the impedance-matching circuits for a single-chip power amplifier (PA) and verifies for 5 GHz-band wireless LAN (IEEE 802.11a) applications. The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverters. One of the advantages of the presented circuits is that it can save on-chip space occupied by the matching circuits compared to that using the spiral inductors, thus reducing the cost. The prototype chip, which consists of PA and matching circuits, is designed employing the presented theory and fabricated. A few of the measured results to verify the design theory are presented.},
keywords={},
doi={10.1093/ietele/e91-c.11.1824},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - Design of 5 GHz-Band Power Amplifier with On-Chip Matching Circuits Using CPW Impedance (K) Inverters
T2 - IEICE TRANSACTIONS on Electronics
SP - 1824
EP - 1827
AU - Ramesh Kumar POKHAREL
AU - Haruichi KANAYA
AU - Keiji YOSHIDA
PY - 2008
DO - 10.1093/ietele/e91-c.11.1824
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2008
AB - This Letter employs transmission-line theory for the impedance-matching circuits for a single-chip power amplifier (PA) and verifies for 5 GHz-band wireless LAN (IEEE 802.11a) applications. The presented matching circuits are composed of conductor-backed coplanar waveguide (CPW) meander-line resonators and impedance (K) inverters. One of the advantages of the presented circuits is that it can save on-chip space occupied by the matching circuits compared to that using the spiral inductors, thus reducing the cost. The prototype chip, which consists of PA and matching circuits, is designed employing the presented theory and fabricated. A few of the measured results to verify the design theory are presented.
ER -