The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta a arquitetura do processador que oferece um nível de confiabilidade muito superior aos atuais. As características são: (1) tolerância a falhas e processamento seguro são integrados em um moderno processador VLSI superescalar; (2) mecanismos leves e eficazes de tolerância a erros leves são propostos e avaliados; (3) erros de temporização em lógica e registros aleatórios são evitados por mecanismos de baixo overhead; (4) o comportamento do programa é ocultado do mundo exterior pelos métodos propostos de tradução de endereços; (5) o vazamento de informações pode ser evitado anexando tags de política para todos os dados e monitorando-os para cada execução de instrução; (6) os ataques de injeção são evitados com uma precisão muito maior do que os sistemas atuais, fornecendo rastreamento de tags; (7) a estrutura geral do processador confiável é proposta com um gerente de confiabilidade que controla a detecção de condições ilegais e volta ao modo normal; e (8) um sistema de teste baseado em FPGA é desenvolvido onde o clock do sistema e a tensão são intencionalmente variados para experimento. O artigo apresenta o esquema fundamental para a confiabilidade, tecnologias elementares para confiabilidade e toda a arquitetura do processador ultraconfiável. Depois de mostrá-los, o artigo conclui com trabalhos futuros.
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Shuichi SAKAI, Masahiro GOSHIMA, Hidetsugu IRIE, "Ultra Dependable Processor" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1386-1393, September 2008, doi: 10.1093/ietele/e91-c.9.1386.
Abstract: This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1386/_p
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@ARTICLE{e91-c_9_1386,
author={Shuichi SAKAI, Masahiro GOSHIMA, Hidetsugu IRIE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Ultra Dependable Processor},
year={2008},
volume={E91-C},
number={9},
pages={1386-1393},
abstract={This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.},
keywords={},
doi={10.1093/ietele/e91-c.9.1386},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - Ultra Dependable Processor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1386
EP - 1393
AU - Shuichi SAKAI
AU - Masahiro GOSHIMA
AU - Hidetsugu IRIE
PY - 2008
DO - 10.1093/ietele/e91-c.9.1386
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - This paper presents the processor architecture which provides much higher level dependability than the current ones. The features of it are: (1) fault tolerance and secure processing are integrated into a modern superscalar VLSI processor; (2) light-weight effective soft-error tolerant mechanisms are proposed and evaluated; (3) timing errors on random logic and registers are prevented by low-overhead mechanisms; (4) program behavior is hidden from the outer world by proposed address translation methods; (5) information leakage can be avoided by attaching policy tags for all data and monitoring them for each instruction execution; (6) injection attacks are avoided with much higher accuracy than the current systems, by providing tag trackings; (7) the overall structure of the dependable processor is proposed with a dependability manager which controls the detection of illegal conditions and recovers to the normal mode; and (8) an FPGA-based testbed system is developed where the system clock and the voltage are intentionally varied for experiment. The paper presents the fundamental scheme for the dependability, elemental technologies for dependability and the whole architecture of the ultra dependable processor. After showing them, the paper concludes with future works.
ER -