The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Os microprocessadores modernos alcançam alto desempenho de aplicação com um nível aceitável de dissipação de energia. Em termos de compensação entre potência e desempenho, a janela de instruções é particularmente importante. Isso ocorre porque aumentar o tamanho da janela atinge alto desempenho, mas o dimensionamento ingênuo da janela de instrução convencional pode aumentar severamente a complexidade e o consumo de energia. Neste artigo, propomos técnicas de janela de instruções de baixo consumo para microprocessadores contemporâneos. Primeiro, o pequeno buffer de reordenação (SROB) reduz a dissipação de energia por meio da alocação diferida e da liberação antecipada. A alocação diferida atrasa a alocação de instruções SROB até que todas as suas dependências de dados sejam resolvidas. Então, as instruções são executadas na ordem do programa e liberadas mais rapidamente do SROB. Isso resulta em maior utilização de recursos e baixo consumo de energia. Em segundo lugar, substituímos uma fila de problemas convencional por uma tabela de consulta direta (DLT) com uma técnica eficiente de tradução de tags. O esquema de tradução resolve a dependência de instruções, especialmente no caso de um produtor para vários consumidores. A eficiência do esquema de tradução decorre do fato de que a grande maioria das dependências de instruções existe dentro de um bloco básico. Resultados experimentais mostram que o projeto proposto reduz significativamente o consumo de energia para benchmarks SPEC2000.
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Min CHOI, Seungryoul MAENG, "An Energy Efficient Instruction Window for Scalable Processor Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1427-1436, September 2008, doi: 10.1093/ietele/e91-c.9.1427.
Abstract: Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1427/_p
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@ARTICLE{e91-c_9_1427,
author={Min CHOI, Seungryoul MAENG, },
journal={IEICE TRANSACTIONS on Electronics},
title={An Energy Efficient Instruction Window for Scalable Processor Architecture},
year={2008},
volume={E91-C},
number={9},
pages={1427-1436},
abstract={Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.},
keywords={},
doi={10.1093/ietele/e91-c.9.1427},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - An Energy Efficient Instruction Window for Scalable Processor Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1427
EP - 1436
AU - Min CHOI
AU - Seungryoul MAENG
PY - 2008
DO - 10.1093/ietele/e91-c.9.1427
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - Modern microprocessors achieve high application performance at the acceptable level of power dissipation. In terms of power to performance trade-off, the instruction window is particularly important. This is because enlarging the window size achieves high performance but naive scaling of the conventional instruction window can severely increase the complexity and power consumption. In this paper, we propose low-power instruction window techniques for contemporary microprocessors. First, the small reorder buffer (SROB) reduces power dissipation by deferred allocation and early release. The deferred allocation delays the SROB allocation of instructions until their all data dependencies are resolved. Then, the instructions are executed in program order and they are released faster from the SROB. This results in higher resource utilization and low power consumption. Second, we replace a conventional issue queue by a direct lookup table (DLT) with an efficient tag translation technique. The translation scheme resolves the instruction dependency, especially for the case of one producer to multiple consumers. The efficiency of the translation scheme stems from the fact that the vast majority of instruction dependency exists within a basic block. Experimental results show that our proposed design reduces the power consumption significantly for SPEC2000 benchmarks.
ER -