The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma estrutura de amostragem e retenção (S/H) de baixa tensão e alta velocidade com excelente eficiência energética. Com base na técnica de amplificador operacional comutado, uma arquitetura inversa que maximiza o fator de feedback é empregada no S/H proposto. Um mecanismo de amostragem dupla insensível à distorção é apresentado para aumentar o rendimento em um fator de dois, ao mesmo tempo que elimina a incompatibilidade de temporização associada aos circuitos de amostragem dupla. Além disso, um amplificador operacional de entrada dupla e saída dupla é proposto para incorporar amostragem dupla no S/H baseado em amplificador operacional comutado. Este amplificador operacional também remove o efeito de memória em circuitos de amostragem dupla e apresenta tempo de ativação rápido para melhorar o desempenho de velocidade em circuitos com amplificador operacional comutado. Os resultados da simulação usando um modelo de processo CMOS de 0.13 µm demonstram que o circuito S/H proposto tem uma distorção harmônica total de -67.3 dB até 250 MSample/s e uma distorção harmônica de 0.8 VPP faixa de entrada com alimentação de 0.8 V. O consumo de energia é de 3.5 mW e a figura de mérito é de apenas 7.4 fJ/passo.
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Hsin-Hung OU, Bin-Da LIU, Soon-Jyh CHANG, "A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1480-1487, September 2008, doi: 10.1093/ietele/e91-c.9.1480.
Abstract: This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3 dB up to 250 MSample/s and a 0.8 VPP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1480/_p
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@ARTICLE{e91-c_9_1480,
author={Hsin-Hung OU, Bin-Da LIU, Soon-Jyh CHANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture},
year={2008},
volume={E91-C},
number={9},
pages={1480-1487},
abstract={This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3 dB up to 250 MSample/s and a 0.8 VPP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.},
keywords={},
doi={10.1093/ietele/e91-c.9.1480},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture
T2 - IEICE TRANSACTIONS on Electronics
SP - 1480
EP - 1487
AU - Hsin-Hung OU
AU - Bin-Da LIU
AU - Soon-Jyh CHANG
PY - 2008
DO - 10.1093/ietele/e91-c.9.1480
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - This paper proposes a low-voltage high-speed sample-and-hold (S/H) structure with excellent power efficiency. Based on the switched-opamp technique, an inverse-flip-around architecture which maximizes the feedback factor is employed in the proposed S/H. A skew-insensitive double-sampling mechanism is presented to increase the throughput by a factor of two while eliminating the timing mismatch associated with double-sampling circuits. Furthermore, a dual-input dual-output opamp is proposed to incorporate double-sampling into the switched-opamp based S/H. This opamp also removes the memory effect in double-sampling circuitry and features fast turn-on time to improve the speed performance in switched-opamp circuits. Simulation results using a 0.13-µm CMOS process model demonstrates the proposed S/H circuit has a total-harmonic-distortion of -67.3 dB up to 250 MSample/s and a 0.8 VPP input range at 0.8 V supply. The power consumption is 3.5 mW and the figure-of-merit is only 7.4 fJ/step.
ER -