The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Dois detectores de fase (PD) são propostos para minimizar o deslocamento de fase e a zona morta quando usados em DLL ou PLL. Com os caminhos de corrida simétricos mais curtos de ambas as entradas, o PD binário consegue uma operação de travamento rápida e eliminação teórica do tempo de configuração. Em contraste com os PDs convencionais cujos deslocamentos são em torno de 10 ps com grande sensibilidade ao dimensionamento, o PD binário proposto mostra um deslocamento de menos de 1 ps com uma redução de 30% no tempo de atraso. A detecção de fase binária do tipo trava proposta também é expandida para formar um PD linear pela adição de um circuito gerador de reset.
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Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM, "Deadzone-Minimized Systematic Offset-Free Phase Detectors" in IEICE TRANSACTIONS on Electronics,
vol. E91-C, no. 9, pp. 1525-1528, September 2008, doi: 10.1093/ietele/e91-c.9.1525.
Abstract: Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e91-c.9.1525/_p
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@ARTICLE{e91-c_9_1525,
author={Young-Sang KIM, Yunjae SUH, Hong-June PARK, Jae-Yoon SIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Deadzone-Minimized Systematic Offset-Free Phase Detectors},
year={2008},
volume={E91-C},
number={9},
pages={1525-1528},
abstract={Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.},
keywords={},
doi={10.1093/ietele/e91-c.9.1525},
ISSN={1745-1353},
month={September},}
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TY - JOUR
TI - Deadzone-Minimized Systematic Offset-Free Phase Detectors
T2 - IEICE TRANSACTIONS on Electronics
SP - 1525
EP - 1528
AU - Young-Sang KIM
AU - Yunjae SUH
AU - Hong-June PARK
AU - Jae-Yoon SIM
PY - 2008
DO - 10.1093/ietele/e91-c.9.1525
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E91-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 2008
AB - Two phase detectors (PD) are proposed to minimize the phase offset and deadzone when used in DLL or PLL. With the shortest symmetrical racing paths from both inputs, the binary PD achieves fast latch operation and theoretical elimination of the setup time. In contrast to the conventional PDs whose offsets are around 10 ps with large sensitivity to sizing, the proposed binary PD shows an offset of less than 1 ps with a reduction of 30-percent delay time. The proposed latch-type binary phase detection is also expanded to form a linear PD by the addition of a reset-generating circuit.
ER -