The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve uma nova técnica de otimização de layout usando simulação eletromagnética (EM). Circuitos equivalentes simples ajustados aos resultados da simulação EM são empregados neste método, para apresentar um guia de modificação para um padrão de layout. Erros de ajuste também são investigados com alguns padrões de layout, a fim de esclarecer o intervalo aplicável do método, pois os erros restringem o intervalo. O método foi adotado com sucesso para um amplificador MMIC de baixo ruído (LNA) de banda X. O padrão de layout do amplificador foi otimizado em apenas dois dias e o amplificador alcançou o desempenho desejado - um ganho de 35 dB e um valor de ruído de 1.7 dB - em um ciclo de desenvolvimento. A área efetiva do chip foi miniaturizada para 4.8 mm2. A área pode ser menor que 70% em comparação com um MMIC de layout convencional.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Shin CHAKI, Yoshinobu SASAKI, Naoto ANDOH, Yasuharu NAKAJIMA, Kazuo NISHITANI, "A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 11, pp. 1960-1967, November 1999, doi: .
Abstract: This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_11_1960/_p
Copiar
@ARTICLE{e82-c_11_1960,
author={Shin CHAKI, Yoshinobu SASAKI, Naoto ANDOH, Yasuharu NAKAJIMA, Kazuo NISHITANI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs},
year={1999},
volume={E82-C},
number={11},
pages={1960-1967},
abstract={This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.},
keywords={},
doi={},
ISSN={},
month={November},}
Copiar
TY - JOUR
TI - A Novel Layout Optimization Technique for Miniaturization and Accurate Design of MMICs
T2 - IEICE TRANSACTIONS on Electronics
SP - 1960
EP - 1967
AU - Shin CHAKI
AU - Yoshinobu SASAKI
AU - Naoto ANDOH
AU - Yasuharu NAKAJIMA
AU - Kazuo NISHITANI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 1999
AB - This paper describes a novel layout optimization technique using electromagnetic (EM) simulation. Simple equivalent circuits fitted to EM simulation results are employed in this method, to present a modification guide for a layout pattern. Fitting errors are also investigated with some layout patterns in order to clarify the applicable range of the method, because the errors restrict the range. The method has been successfully adopted to an X-band low noise MMIC amplifier (LNA). The layout pattern of the amplifier was optimized in only two days and the amplifier has achieved target performances--a 35 dB gain and a 1.7 dB noise figure--in one development cycle. The effective chip area has been miniaturized to 4.8 mm2. The area could be smaller than 70% in comparison with a conventional layout MMIC.
ER -