The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um novo divisor de ponto flutuante (FDIV), no qual os principais recursos de circuitos binários redundantes e um esquema de relógio assíncrono reduzem o tempo de atraso e a penalidade de área. A representação binária redundante de +1 = (1, 0), 0 = (0, 0), -1 = (0,1) é aplicada a todos os circuitos de divisão de mantissa. A representação simples e unificada reduz o atraso do circuito para a determinação do quociente. Além disso, o circuito gerador de clock local para o esquema de clock assíncrono elimina a sobrecarga de margem de clock. O circuito gerador garante a pior operação de tempo de atraso pelo circuito de feedback dos caminhos de atraso de réplica através de um elemento C. A operação iterativa interna pelo esquema assíncrono e o circuito de adição/subtração binário redundante modificado mantêm a área pequena. O desenho da arquitetura evita tempo extra de cálculo para os pós-processos, cuja principal função é produzir as flags de status em ponto flutuante. O núcleo FDIV usando tecnologias propostas opera a 42 ns com tecnologia CMOS de 1 µm e interconexões triplas de metal. O pequeno núcleo de transistores de 0.35 k é disposto em um formato de 13.5 µm
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Hiroaki SUZUKI, Hiroshi MAKINO, Koichiro MASHIKO, "A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 1, pp. 105-110, January 1999, doi: .
Abstract: This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_1_105/_p
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@ARTICLE{e82-c_1_105,
author={Hiroaki SUZUKI, Hiroshi MAKINO, Koichiro MASHIKO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme},
year={1999},
volume={E82-C},
number={1},
pages={105-110},
abstract={This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - A Floating-Point Divider Using Redundant Binary Circuits and an Asynchronous Clock Scheme
T2 - IEICE TRANSACTIONS on Electronics
SP - 105
EP - 110
AU - Hiroaki SUZUKI
AU - Hiroshi MAKINO
AU - Koichiro MASHIKO
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 1999
AB - This paper describes a new floating-point divider (FDIV), in which the key features of redundant binary circuits and an asynchronous clock scheme reduce the delay time and area penalty. The redundant binary representation of +1 = (1, 0), 0 = (0, 0), -1 = (0,1) is applied to the all mantissa division circuits. The simple and unified representation reduces circuit delay for the quotient determination. Additionally, the local clock generator circuit for the asynchronous clock scheme eliminates clock margin overhead. The generator circuit guarantees the worst delay-time operation by the feedback loop of the replica delay paths via a C-element. The internal iterative operation by the asynchronous scheme and the modified redundant-binary addition/subtraction circuit keep the area small. The architecture design avoids extra calculation time for the post processes, whose main role is to produce the floating-point status flags. The FDIV core using proposed technologies operates at 42. 1 ns with 0.35 µm CMOS technology and triple metal interconnections. The small core of 13.5 k transistors is laid-out in a 730µm
ER -