The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
À medida que a comunicação sem fio está penetrando em todos os cantos do globo, o design ideal e a análise precisa de RF, dispositivos semicondutores de potência tornam-se um dos maiores desafios no desenvolvimento de ferramentas EDA e TCAD (Tecnologia CAD). O medidor de desempenho para esses dispositivos é bastante diferente daquele para dispositivos digitais ou analógicos destinados a aplicações de pequenos sinais, pois o ganho de potência, a eficiência e a distorção (ou a faixa de linearidade) são as maiores preocupações do projeto. Neste artigo, são discutidas a metodologia e os fundamentos matemáticos para análise numérica de grandes distorções de sinal no nível de simulação de dispositivos. Embora o método de equilíbrio harmônico (HB) tenha sido usado há muito tempo na simulação de circuitos para análise de grandes distorções de sinal, a implementação do mesmo método na simulação de dispositivos enfrenta desafios assustadores, entre os quais estão o tremendo custo computacional e o gerenciamento de armazenamento de memória. Mas os benefícios de conduzir tal simulação em nível de dispositivo também são óbvios – pela primeira vez, o impacto da tecnologia e da variação estrutural do dispositivo no desempenho de grandes sinais pode ser avaliado diretamente. As etapas necessárias para tornar a análise HB viável na simulação de dispositivos são descritas e a melhoria algorítmica para aliviar a carga de computação/armazenamento é discutida. As aplicações do simulador de dispositivos para vários dispositivos de potência de RF, incluindo GaAs MESFETs e LDMOS de silício (MOS de difusão lateral), são apresentadas, e os insights obtidos com tal análise são fornecidos.
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Zhiping YU, Robert W. DUTTON, Boris TROYANOSKY, Junko SATO-IWANAGA, "Large Signal Analysis of RF Circuits in Device Simulation" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 6, pp. 908-916, June 1999, doi: .
Abstract: As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_6_908/_p
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@ARTICLE{e82-c_6_908,
author={Zhiping YU, Robert W. DUTTON, Boris TROYANOSKY, Junko SATO-IWANAGA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Large Signal Analysis of RF Circuits in Device Simulation},
year={1999},
volume={E82-C},
number={6},
pages={908-916},
abstract={As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Large Signal Analysis of RF Circuits in Device Simulation
T2 - IEICE TRANSACTIONS on Electronics
SP - 908
EP - 916
AU - Zhiping YU
AU - Robert W. DUTTON
AU - Boris TROYANOSKY
AU - Junko SATO-IWANAGA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 1999
AB - As wireless communication is penetrating every corner of the globe, the optimum design and accurate analysis of RF, power semiconductor devices become one of the biggest challenges in EDA and TCAD (Technology CAD) tool development. The performance gauge for these devices is quite different from that for either digital or analog devices aimed at small-signal applications in that the power gain, efficiency, and distortion (or the range of linearity) are the utmost design concerns. In this article, the methodology and mathematical foundation for numerical analysis of large signal distortion at the device simulation level are discussed. Although the harmonic balance (HB) method has long been used in circuit simulation for large signal distortion analysis, the implementation of the same method in device simulation faces daunting challenges, among which are the tremendous computational cost and memory storage management. But the benefits from conducting such a device level simulation are also obvious--for the first time, the impact of technology and structural variation of device on large signal performance can directly be assessed. The necessary steps to make the HB analysis feasible in device simulation are outlined and algorithmic improvement to ease the computation/storage burden is discussed. The applications of the device simulator for various RF power devices, including GaAs MESFETs and silicon LDMOS (lateral diffusion MOS) are presented, and the insight gained from such an analysis is provided.
ER -