The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Desenvolvemos um novo tipo de sintetizador digital direto de interpolação de fase (DDS) com um gerador de atraso estruturado simetricamente. O novo DDS é semelhante a um DDS de saída senoidal, pois produz sinais espúrios mais baixos, mas não requer uma tabela de consulta senoidal. O gerador de atraso estruturado simetricamente reduz o jitter periódico no bit mais significativo (MSB) do acumulador DDS. A estrutura simétrica permite que o gerador de atraso produza um tempo de atraso altamente preciso e elimine a necessidade de ajustar as constantes do circuito. Resultados experimentais confirmam a operação do sintetizador de frequência na qual o nível do sinal espúrio é reduzido a menos que o do acumulador.
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Hideyuki NOSAKA, Tadao NAKAGAWA, Akihiro YAMAGISHI, "A Phase Interpolation Direct Digital Synthesizer with a Symmetrically Structured Delay Generator" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 7, pp. 1067-1072, July 1999, doi: .
Abstract: We have developed a new type of phase interpolation direct digital synthesizer (DDS) with a symmetrically structured delay generator. The new DDS is similar to a sine output DDS in that it produces lower spurious signals, but it does not require a sine look-up table. The symmetrically structured delay generator reduces the periodic jitter in the most significant bit (MSB) of the DDS accumulator. The symmetrical structure enables the delay generator to produce highly accurate delay timing and eliminates the need to adjust the circuit constants. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_7_1067/_p
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@ARTICLE{e82-c_7_1067,
author={Hideyuki NOSAKA, Tadao NAKAGAWA, Akihiro YAMAGISHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Phase Interpolation Direct Digital Synthesizer with a Symmetrically Structured Delay Generator},
year={1999},
volume={E82-C},
number={7},
pages={1067-1072},
abstract={We have developed a new type of phase interpolation direct digital synthesizer (DDS) with a symmetrically structured delay generator. The new DDS is similar to a sine output DDS in that it produces lower spurious signals, but it does not require a sine look-up table. The symmetrically structured delay generator reduces the periodic jitter in the most significant bit (MSB) of the DDS accumulator. The symmetrical structure enables the delay generator to produce highly accurate delay timing and eliminates the need to adjust the circuit constants. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - A Phase Interpolation Direct Digital Synthesizer with a Symmetrically Structured Delay Generator
T2 - IEICE TRANSACTIONS on Electronics
SP - 1067
EP - 1072
AU - Hideyuki NOSAKA
AU - Tadao NAKAGAWA
AU - Akihiro YAMAGISHI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 1999
AB - We have developed a new type of phase interpolation direct digital synthesizer (DDS) with a symmetrically structured delay generator. The new DDS is similar to a sine output DDS in that it produces lower spurious signals, but it does not require a sine look-up table. The symmetrically structured delay generator reduces the periodic jitter in the most significant bit (MSB) of the DDS accumulator. The symmetrical structure enables the delay generator to produce highly accurate delay timing and eliminates the need to adjust the circuit constants. Experimental results confirm frequency synthesizer operation in which the spurious signal level is reduced to less than that of the accumulator.
ER -