The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É descrito um esquema lógico dinâmico NMOS de 4 fases, que se destina a atingir baixo consumo de energia no projeto submícron profundo. Neste esquema, a corrente de curto-circuito é eliminada e, além disso, a oscilação de tensão dos sinais de transição é reduzida, resultando no aumento eficaz da redução de potência. Primeiro, são especificadas características distintivas desta lógica dinâmica de 4 fases, em comparação com a lógica CMOS estática e a lógica CMOS dominó dinâmica. Em seguida, são tentadas simulações de potência para a lógica dinâmica de 4 fases, lógica CMOS estática, lógica CMOS dinâmica e lógica de transistor de passagem, usando uma série de módulos lógicos, que demonstram que a lógica dinâmica de 4 fases NMOS é a mais potência -eficiente. Além disso, através da simulação de atraso de porta, também é discutida a capacidade de quantos transistores podem ser empacotados em um bloco lógico.
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Bao-Yu SONG, Makoto FURUIE, Yukihiro YOSHIDA, Takao ONOYE, Isao SHIRAKAWA, "Low-Power Scheme of NMOS 4-Phase Dynamic Logic" in IEICE TRANSACTIONS on Electronics,
vol. E82-C, no. 9, pp. 1772-1776, September 1999, doi: .
Abstract: An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e82-c_9_1772/_p
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@ARTICLE{e82-c_9_1772,
author={Bao-Yu SONG, Makoto FURUIE, Yukihiro YOSHIDA, Takao ONOYE, Isao SHIRAKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Power Scheme of NMOS 4-Phase Dynamic Logic},
year={1999},
volume={E82-C},
number={9},
pages={1772-1776},
abstract={An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Low-Power Scheme of NMOS 4-Phase Dynamic Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 1772
EP - 1776
AU - Bao-Yu SONG
AU - Makoto FURUIE
AU - Yukihiro YOSHIDA
AU - Takao ONOYE
AU - Isao SHIRAKAWA
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E82-C
IS - 9
JA - IEICE TRANSACTIONS on Electronics
Y1 - September 1999
AB - An NMOS 4-phase dynamic logic scheme is described, which is intended to achieve low-power consumption in the deep submicron design. In this scheme, the short-circuit current is eliminated, and moreover, the voltage swing of transition signals is reduced, resulting in enhancing power reduction effectively. First, distinctive features of this 4-phase dynamic logic are specified, as compared with the static CMOS logic and dynamic domino CMOS logic. Then, power simulations are attempted for the 4-phase dynamic logic, static CMOS logic, dynamic CMOS logic, and pass-transistor logic, by using a number of logic modules, which demonstrate that the NMOS 4-phase dynamic logic is the most power-efficient. Moreover, through the gate delay simulation, the capability of how many transistors can be packed in a logic block is also discussed.
ER -