The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo trata de um novo esquema de clock de baixa potência para circuitos lógicos dinâmicos para reduzir a dissipação de energia. Embora os esquemas de clock convencionais para circuitos lógicos dinâmicos sejam usados principalmente para aplicações de alta velocidade, como circuitos dominó, sua corrente de pico é muito grande devido à concentração de pré-carga e descarga em um curto período. É difícil para esses esquemas conseguir reduções na dissipação de energia e alto desempenho ao mesmo tempo. No campo da engenharia de energia, nivelar a potência significa diminuir pico a pico de potência mantendo sua quantidade. Assim, propomos um esquema de clock sofisticado que nivela a dissipação de energia dos elementos de processamento que reduz principalmente a dissipação de energia dos drivers de clock. Nosso esquema de clock proposto usa um clock sobreposto com um controle de potência refinado, e a corrente de pico torna-se mais baixa e a dissipação de energia em um curto período é nivelada sem penalidade no desempenho da velocidade. Nosso esquema proposto é aplicado a um multiplicador de matriz de 4 bits, e as reduções de dissipação de energia do multiplicador e do driver de clock são medidas pelo simulador HSPICE baseado na tecnologia CMOS de 0.5 µm. É mostrado que a dissipação de energia dos drivers de clock, do multiplicador de matriz de 4 bits e do total é reduzida em cerca de 13.2%, 2.6% e 7.0%, respectivamente. Como resultado, nosso esquema de clock é eficaz na redução das dissipações de energia dos drivers de clock.
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Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, "A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 11, pp. 1733-1738, November 2000, doi: .
Abstract: This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_11_1733/_p
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@ARTICLE{e83-c_11_1733,
author={Hiroyuki MATSUBARA, Takahiro WATANABE, Tadao NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits},
year={2000},
volume={E83-C},
number={11},
pages={1733-1738},
abstract={This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.},
keywords={},
doi={},
ISSN={},
month={November},}
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TY - JOUR
TI - A Clocking Scheme for Lowering Peak-Current in Dynamic Logic Circuits
T2 - IEICE TRANSACTIONS on Electronics
SP - 1733
EP - 1738
AU - Hiroyuki MATSUBARA
AU - Takahiro WATANABE
AU - Tadao NAKAMURA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2000
AB - This paper deals with a new low-power clocking scheme for dynamic logic circuits to reduce power dissipation. Although conventional clocking schemes for dynamic logic circuits are mainly used for high-speed applications like domino circuits, their peak-current are very large due to the concentration of precharging and discharging in a short period. It is hard for these schemes to accomplish both reductions of power dissipation and high performance at the same time. In the field of power engineering, leveling power means decreasing peak-to-peak of power keeping its amount. So, we propose a sophisticated clocking scheme leveling power dissipation of processing elements that mainly reduces power dissipation of clock drivers. Our proposed clocking scheme uses an over-lapped clock with a fine-grain power control, and peak-current becomes lower and power dissipation in short period is leveled without penalty of speed performance. Our proposed scheme is applied to a 4-bit array multiplier, and reductions of power dissipation of both the multiplier and clock driver are measured by the HSPICE simulator based on 0.5 µm CMOS technology. It is shown that power dissipation of clock drivers, 4-bit array multiplier, and the total are reduced by about 13.2 percent, 2.6 percent and 7.0 percent, respectively. As a result, our clocking scheme is effective in reduction of power dissipations of clock drivers.
ER -