The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma nova abordagem para alcançar alto desempenho e baixo consumo de energia para caches associativos de conjunto. A cache, chamada cache associativo de conjunto de previsão de caminho, seleciona especulativamente uma única via, que provavelmente conterá os dados desejados pelo processador, do conjunto designado por um endereço de memória, antes de iniciar um acesso normal ao cache. Ao acessar apenas a única via prevista, em vez de acessar todas as vias de um conjunto, o consumo de energia pode ser reduzido. Para que o cache de previsão de caminho tenha um bom desempenho, a precisão da previsão de caminho é importante. Este artigo mostra que a precisão de uma previsão de caminho baseada em MRU (usada mais recentemente) é superior a 90% para a maioria dos programas de benchmark. O cache de previsão de caminho proposto melhora o produto ED (atraso de energia) em 60-70% em comparação com o cache associativo de conjunto convencional.
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Koji INOUE, Tohru ISHIHARA, Kazuaki MURAKAMI, "A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 186-194, February 2000, doi: .
Abstract: This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_186/_p
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@ARTICLE{e83-c_2_186,
author={Koji INOUE, Tohru ISHIHARA, Kazuaki MURAKAMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection},
year={2000},
volume={E83-C},
number={2},
pages={186-194},
abstract={This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A High-Performance and Low-Power Cache Architecture with Speculative Way-Selection
T2 - IEICE TRANSACTIONS on Electronics
SP - 186
EP - 194
AU - Koji INOUE
AU - Tohru ISHIHARA
AU - Kazuaki MURAKAMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - This paper proposes a new approach to achieving high performance and low energy consumption for set-associative caches. The cache, called way-predicting set-associative cache, speculatively selects a single way, which is likely to contain the data desired by the processor, from the set designated by a memory address, before it starts a normal cache access. By accessing only the single way predicted, instead of accessing all the ways in a set, energy consumption can be reduced. In order for the way-predicting cache to perform well, accuracy of way prediction is important. This paper shows that the accuracy of an MRU (most recently used)-based way prediction is higher than 90% for most of the benchmark programs. The proposed way-predicting cache improves the ED (energy-delay) product by 60-70% compared to the conventional set-associative cache.
ER -