The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Vários tipos de arquitetura de alta largura de banda usando a tecnologia DRAM incorporada foram apresentados anteriormente. Na maioria dos casos, eles usam implementação de barramento amplo e/ou velocidade de barramento rápida, que acarretam a penalidade de área da matriz e muito consumo de energia ao mesmo tempo. O barramento de leitura-modificação-gravação de terminação única proposto aumenta a largura de banda duas vezes mais, enquanto mantém o mesmo tamanho e velocidade do barramento. O barramento de dados compreende um barramento de leitura de 1 k bits e um barramento de gravação de 1 k bits, cada um trabalhando simultaneamente e tem amplitude de 0 V a 1 V, portanto, o consumo de energia medido é de apenas 0.3 W a uma frequência de 166 MHz. . Um tamanho de página programável reduz a taxa de erros de página e melhora eficientemente a largura de banda que é comparável ao barramento amplo e abordagem de velocidade rápida. Todos os recursos propostos são implementados em um buffer de quadros 3D para atingir largura de banda de 42.4 G-BPS.
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Kazunari INOUE, Hideaki ABE, Kaori MORI, Shuji FUKAGAWA, "A Low-Voltage 42.4 G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 195-204, February 2000, doi: .
Abstract: Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_195/_p
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@ARTICLE{e83-c_2_195,
author={Kazunari INOUE, Hideaki ABE, Kaori MORI, Shuji FUKAGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Low-Voltage 42.4 G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer},
year={2000},
volume={E83-C},
number={2},
pages={195-204},
abstract={Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A Low-Voltage 42.4 G-BPS Single-Ended Read-Modify-Write Bus and Programmable Page-Size on a 3D Frame-Buffer
T2 - IEICE TRANSACTIONS on Electronics
SP - 195
EP - 204
AU - Kazunari INOUE
AU - Hideaki ABE
AU - Kaori MORI
AU - Shuji FUKAGAWA
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - Various kinds of high bandwidth architecture using the embedded DRAM technology have been presented previously. In most cases, they use wide bus implementation and/or fast bus speed, that both have the penalty of die area and much power consumption at the same time. The proposing single-ended read-modify-write bus increases the bandwidth twice as high, while it maintains the same bus size and the same bus speed. The data-bus comprises 1 k-bit read-bus and 1 k-bit write-bus that each works concurrently, and has amplitude from 0 V to 1 V, hence the measured power consumption is only 0.3 W at a frequency of 166 MHz. A programmable page-size reduces the page miss-rate and efficiently improves the bandwidth that is comparable to the wide bus and fast speed approach. All the proposing features are implemented on a 3D frame-buffer to achieve 42.4 G-BPS bandwidth.
ER -