The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um conversor A/D cíclico multibit de 10 Mamostras/s de 3 bits para LSIs de sinal misto com uma pequena área de chip de 1.5 mm2 e baixo consumo de energia de 10.8 mW com fonte de alimentação de 2.7 V foi obtido usando um processo CMOS de 0.8 µm. Este módulo ADC foi projetado para LSIs servocontroladores de alta velocidade usados em sistemas de unidade de disco rígido. Descobrimos que a conversão cíclica de três ciclos (quatro bits, três bits+(um bit redundante) e três bits+(um bit redundante)) era ideal para obter resolução de 10 bits com uma pequena área de chip e baixo consumo de energia, dada a necessidade. tempo de conversão de 0.33 µs. Nossa arquitetura multipath reduziu o consumo de energia em 30% em comparação com conversores A/D cíclicos convencionais. Ao adicionar um caminho de sinal entre o amplificador residual e o subADC de quatro bits, o requisito de tempo de estabilização pode ser relaxado e o consumo de energia do amplificador assim reduzido.
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Tatsuji MATSUURA, Akihiro KITAGAWA, Toshiro TSUKADA, Eiki IMAIZUMI, "A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 2, pp. 227-235, February 2000, doi: .
Abstract: A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_2_227/_p
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@ARTICLE{e83-c_2_227,
author={Tatsuji MATSUURA, Akihiro KITAGAWA, Toshiro TSUKADA, Eiki IMAIZUMI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC},
year={2000},
volume={E83-C},
number={2},
pages={227-235},
abstract={A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A 10-bit 3-Msample/s CMOS Multipath Multibit Cyclic ADC
T2 - IEICE TRANSACTIONS on Electronics
SP - 227
EP - 235
AU - Tatsuji MATSUURA
AU - Akihiro KITAGAWA
AU - Toshiro TSUKADA
AU - Eiki IMAIZUMI
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2000
AB - A 10-bit 3-Msample/s multibit cyclic A/D converter for mixed-signal LSIs with a small chip-area of 1.5 mm2 and low power consumption of 10.8 mW with a 2.7-V power supply was realized using a 0.8-µm CMOS process. This ADC module is designed for high-speed servo-controller LSIs used in hard-disk-drive systems. We found that three-cycle cyclic conversion (four bit, three bit+(one redundant bit), and three bit+(one redundant bit)) was optimal for achieving 10-bit resolution with a small chip-area and low power consumption given a required conversion time of 0.33 µs. Our multipath architecture cut power consumption by 30% compared to conventional cyclic A/D converters. By adding one signal path between the residue amplifier and the four bit subADC, the settling timing requirement can be relaxed, and the amplifier's power consumption thus reduced.
ER -