The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A tecnologia SOI parcialmente esgotada com isolamento de trincheira híbrida amarrada ao corpo foi desenvolvida para neutralizar os efeitos do corpo flutuante que oferecem impacto negativo na corrente de acionamento dos transistores e na estabilidade da operação do circuito, mantendo os méritos específicos da SOI, como operação em alta velocidade e baixo consumo de energia. . A viabilidade desta tecnologia e seus efeitos superiores de erros suaves foram demonstrados por uma SRAM de 4 M bits totalmente funcional. Suas características de radiofrequência também foram avaliadas e verificou-se que transistores de alto desempenho e elementos passivos podem ser realizados pela combinação da estrutura SOI e um substrato de alta resistividade. Além disso, também foi demonstrada sua aplicação a um IC digital de 2.5 GHz para comunicação óptica. Assim, foi comprovado que os dispositivos SOI acoplados ao corpo com isolamento de trincheira híbrido são adequados para realizar sistemas em um chip de alta velocidade, inteligentes e confiáveis, integrando vários IPs.
Yasuo YAMAGUCHI
Takashi IPPOSHI
Kimio UEDA
Koichiro MASHIKO
Shigeto MAEGAWA
Masahide INUISHI
Tadashi NISHIMURA
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Yasuo YAMAGUCHI, Takashi IPPOSHI, Kimio UEDA, Koichiro MASHIKO, Shigeto MAEGAWA, Masahide INUISHI, Tadashi NISHIMURA, "Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 12, pp. 1735-1745, December 2001, doi: .
Abstract: Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_12_1735/_p
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@ARTICLE{e84-c_12_1735,
author={Yasuo YAMAGUCHI, Takashi IPPOSHI, Kimio UEDA, Koichiro MASHIKO, Shigeto MAEGAWA, Masahide INUISHI, Tadashi NISHIMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application},
year={2001},
volume={E84-C},
number={12},
pages={1735-1745},
abstract={Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Partially Depleted SOI Technology with Body-Tied Hybrid Trench Isolation for High-Speed System-On-a-Chip Application
T2 - IEICE TRANSACTIONS on Electronics
SP - 1735
EP - 1745
AU - Yasuo YAMAGUCHI
AU - Takashi IPPOSHI
AU - Kimio UEDA
AU - Koichiro MASHIKO
AU - Shigeto MAEGAWA
AU - Masahide INUISHI
AU - Tadashi NISHIMURA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 12
JA - IEICE TRANSACTIONS on Electronics
Y1 - December 2001
AB - Partially depleted SOI technology with body-tied hybrid trench isolation was developed in order to counteract floating body effects which offers negative impact on the drive current of transistors and the stability of circuit operation while maintaining SOI's specific merits such as high speed operation and low power consumption. The feasibility of this technology and its superior soft error effects were demonstrated by a fully functional 4M-bit SRAM. Its radio frequency characteristics were also evaluated and it was verified that high-performance transistors and passive elements can be realized by the combination of the SOI structure and a high-resistivity substrate. Moreover, its application to a 2.5 GHz digital IC for optical communication was also demonstrated. Thus it was proven that the body-tied SOI devices with the hybrid trench isolation is suitable to realize intelligent and reliable high-speed system-on-a chip integrating various IP's.
ER -