The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve um esquema de teste de memória de acesso aleatório (RAM, às vezes também chamado de array) que possui os seguintes atributos: (1) Pode ser usado tanto no modo integrado quanto no modo off chip/módulo. (2) Pode ser usado para testar e diagnosticar matrizes nuas. (3) O diagnóstico de falhas é simples e “gratuito” para algumas falhas durante o teste. (4) Nunca está sujeito a alias. (5) Dependendo da duração do teste, ele pode detectar muitos tipos de falhas, como células presas, falhas de decodificador, curtos, sensibilidade a padrões, etc. (6) Se usado como recurso integrado, não desacelera o operação normal da matriz. (7) Não requer armazenamento de respostas corretas. Um único bit de resposta sempre indica se uma falha foi detectada. Assim, o requisito de armazenamento para a implementação do esquema de teste é zero. (8) Se usado como um recurso integrado, a sobrecarga de hardware é muito baixa.
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Jacob SAVIR, "RAM BIST" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 1, pp. 102-107, January 2001, doi: .
Abstract: This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: (1) Can be used in both built-in mode and off chip/module mode. (2) Can be used to test and diagnose naked arrays. (3) Fault diagnosis is simple and is "free" for some faults during test. (4) Is never subject to aliasing. (5) Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. (6) If used as built-in feature, it does not slow down the normal operation of the array. (7) Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. (8) If used as a built-in feature, the hardware overhead is very low.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_1_102/_p
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@ARTICLE{e84-c_1_102,
author={Jacob SAVIR, },
journal={IEICE TRANSACTIONS on Electronics},
title={RAM BIST},
year={2001},
volume={E84-C},
number={1},
pages={102-107},
abstract={This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: (1) Can be used in both built-in mode and off chip/module mode. (2) Can be used to test and diagnose naked arrays. (3) Fault diagnosis is simple and is "free" for some faults during test. (4) Is never subject to aliasing. (5) Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. (6) If used as built-in feature, it does not slow down the normal operation of the array. (7) Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. (8) If used as a built-in feature, the hardware overhead is very low.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - RAM BIST
T2 - IEICE TRANSACTIONS on Electronics
SP - 102
EP - 107
AU - Jacob SAVIR
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 1
JA - IEICE TRANSACTIONS on Electronics
Y1 - January 2001
AB - This paper describes a random access memory (RAM, sometimes also called an array) test scheme that has the following attributes: (1) Can be used in both built-in mode and off chip/module mode. (2) Can be used to test and diagnose naked arrays. (3) Fault diagnosis is simple and is "free" for some faults during test. (4) Is never subject to aliasing. (5) Depending upon the test length, it can detect many kinds of failures, like stuck-cells, decoder faults, shorts, pattern-sensitive, etc. (6) If used as built-in feature, it does not slow down the normal operation of the array. (7) Does not require storage of correct responses. A single response bit always indicates whether a fault has been detected. Thus, the storage requirement for the implementation of the test scheme is zero. (8) If used as a built-in feature, the hardware overhead is very low.
ER -