The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É relatado um demodulador ULSI completo de phase shift keying (PSK) multiformato de chip único para transmissão digital BS japonesa. O sistema de recuperação de portadora mostra a faixa de pull-in de até +/-5 MHz. O sistema de recuperação de clock cancela a característica de atraso de grupo ruim e a degradação da ortogonalidade causada pelo front-end analógico e melhora o desempenho do BER em 0.2 dB. Assim, a exigência do front-end analógico é relaxada. Um PLL digital garante jitter mínimo de referência de clock do programa no fluxo de dados de saída, o que simplifica o gerenciamento de jitter no decodificador de sistema MPEG2 seguinte. Ele integra dois ADCs de 8 MHz de 60 bits, VCO de 58 MHz, SRAM de 1 Mbit e o núcleo demodulador FEC de 450 K-gate. A implementação de RAM desintercaladora de 1 Mbit facilita o uso de um receptor de baixo custo. O chip de transistor de 8.8 milhões ocupa os 72 mm2 em uma tecnologia CMOS de metal triplo de 0.25 µm.
Eiji ARITA
Takashi FUJIWARA
Kin-ichiro NISHIYAMA
Akiko MAENO
Yasuo MATSUNAMI
Masahiko NAKAMURA
Hirohisa MACHIDA
Shuji MURAKAMI
Hiroyuki NAKAYAMA
Masahiko YOSHIMOTO
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Eiji ARITA, Takashi FUJIWARA, Kin-ichiro NISHIYAMA, Akiko MAENO, Yasuo MATSUNAMI, Masahiko NAKAMURA, Hirohisa MACHIDA, Shuji MURAKAMI, Hiroyuki NAKAYAMA, Masahiko YOSHIMOTO, "A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 166-174, February 2001, doi: .
Abstract: A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm2 in a 0.25 µm triple-metal CMOS technology.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_166/_p
Copiar
@ARTICLE{e84-c_2_166,
author={Eiji ARITA, Takashi FUJIWARA, Kin-ichiro NISHIYAMA, Akiko MAENO, Yasuo MATSUNAMI, Masahiko NAKAMURA, Hirohisa MACHIDA, Shuji MURAKAMI, Hiroyuki NAKAYAMA, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite},
year={2001},
volume={E84-C},
number={2},
pages={166-174},
abstract={A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm2 in a 0.25 µm triple-metal CMOS technology.},
keywords={},
doi={},
ISSN={},
month={February},}
Copiar
TY - JOUR
TI - A Dynamically Configurable Multi-Format PSK Demodulator for Digital HDTV Using Broadcasting-Satellite
T2 - IEICE TRANSACTIONS on Electronics
SP - 166
EP - 174
AU - Eiji ARITA
AU - Takashi FUJIWARA
AU - Kin-ichiro NISHIYAMA
AU - Akiko MAENO
AU - Yasuo MATSUNAMI
AU - Masahiko NAKAMURA
AU - Hirohisa MACHIDA
AU - Shuji MURAKAMI
AU - Hiroyuki NAKAYAMA
AU - Masahiko YOSHIMOTO
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A complete single chip multi-format Phase Shift Keying (PSK) demodulator ULSI for Japanese BS digital broadcasting is reported. The carrier recovery system shows the pull-in range up to +/-5 MHz. The clock recovery system cancels the poor group delay characteristic and the orthogonality degradation caused by the analog front end, and improves the BER performance by 0.2 dB. Thus the requirement to the analog front end is relaxed. A digital PLL ensures minimum program clock reference jitter in the output data stream, which simplifies jitter management in the succeeding MPEG2 system decoder. It integrates two 8-bit 60 MHz ADCs, 58 MHz VCO, 1 Mbit SRAM and the 450 K-gate FEC-demodulator core. Implementation of 1 Mbit de-interleaver RAM facilitates the use of a low cost receiver. The 8.8 milion transistor chip occupies the 72 mm2 in a 0.25 µm triple-metal CMOS technology.
ER -