The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Apresentamos um caso de projeto e implementação de um receptor QPSK (Quaternary Phase Shift Keying) de alta velocidade. Como a modulação PSK transporta suas informações através da fase, o receptor digital de banda base pode recuperar o símbolo transmitido da fase recebida. O receptor implementado estima o tempo do símbolo e o deslocamento de frequência usando dados amostrados de mais de 32 símbolos sem informações de símbolo transmitidas, e a RAM incorporada é usada para o atraso da fase recebida durante o tempo de estimativa. O receptor é implementado usando cerca de 92,000 portas da biblioteca Samsung KG75 SOG que usa tecnologia CMOS de 0.65 µm. O resultado do teste do chip fabricado mostra que o receptor opera a uma taxa de clock de 40 MHz em 5.6 V, o que equivale à taxa de dados de 40 Mbps.
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Seung-Geun KIM, Wooncheol HWANG, Youngsun KIM, Youngkou LEE, Sungsoo CHOI, Kiseon KIM, "Fully Digital Preambleless 40 Mbps QPSK Receiver for Burst Transmission" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 175-182, February 2001, doi: .
Abstract: We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_175/_p
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@ARTICLE{e84-c_2_175,
author={Seung-Geun KIM, Wooncheol HWANG, Youngsun KIM, Youngkou LEE, Sungsoo CHOI, Kiseon KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Fully Digital Preambleless 40 Mbps QPSK Receiver for Burst Transmission},
year={2001},
volume={E84-C},
number={2},
pages={175-182},
abstract={We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Fully Digital Preambleless 40 Mbps QPSK Receiver for Burst Transmission
T2 - IEICE TRANSACTIONS on Electronics
SP - 175
EP - 182
AU - Seung-Geun KIM
AU - Wooncheol HWANG
AU - Youngsun KIM
AU - Youngkou LEE
AU - Sungsoo CHOI
AU - Kiseon KIM
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - We present a case of design and implementation of a high-speed burst QPSK (Quaternary Phase Shift Keying) receiver. Since the PSK modulation carries its information through the phase, the baseband digital receiver can recover transmitted symbol from the received phase. The implemented receiver estimates symbol time and frequency offset using sampled data over 32 symbols without transmitted symbol information, and embedded RAM is used for received phase delay over estimation time. The receiver is implemented using about 92,000 gates of Samsung KG75 SOG library which uses 0.65 µm CMOS technology. The fabricated chip test result shows that the receiver operates at 40 MHz clock rate on 5.6 V, which is equivalent to the 40 Mbps data rate.
ER -