The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É descrito um chip que integra dois núcleos de processador multimídia VLIW com um mecanismo de streaming de hardware. Pode implementar um videofone em tempo real ou um codec MPEG4. Cada núcleo do processador possui recursos idênticos e compartilha a memória e as unidades de interface de E/S do sistema. Com sua estrutura simétrica, os aplicativos podem ser executados em qualquer processador sem restrições. Para acelerar aplicações específicas de multimídia, a arquitetura deste processador possui diversos recursos. Ele mescla os recursos de um RISC e um DSP, seu conjunto de instruções é estendido para acelerar aplicações de vídeo e áudio e suporta um sistema de memória embarcado eficiente, para reduzir a largura de banda e a latência para aplicações multimídia que necessitam de acessos frequentes à memória. O tamanho do chip será de 100 mm2 matriz que contém portas lógicas de 700 K, 60 KB de RAM e 16 KB de ROM, em uma tecnologia de célula padrão CMOS de 0.25 µm. Na frequência operacional de 65 MHz, ele pode processar codificação de vídeo H.263 a 15 quadros/s CIF e codificação de áudio G.723.1 com alocação de tempo de processamento de 80%.
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Jeong-Min KIM, Yun-Su SHIN, In-Gu HWANG, Kwang-Sun LEE, Sang-Il HAN, Sang-Gyu PARK, Soo-Ik CHAE, "A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 2, pp. 183-192, February 2001, doi: .
Abstract: A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_2_183/_p
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@ARTICLE{e84-c_2_183,
author={Jeong-Min KIM, Yun-Su SHIN, In-Gu HWANG, Kwang-Sun LEE, Sang-Il HAN, Sang-Gyu PARK, Soo-Ik CHAE, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores},
year={2001},
volume={E84-C},
number={2},
pages={183-192},
abstract={A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - A High-Performance Videophone Chip with Dual Multimedia VLIW Processor Cores
T2 - IEICE TRANSACTIONS on Electronics
SP - 183
EP - 192
AU - Jeong-Min KIM
AU - Yun-Su SHIN
AU - In-Gu HWANG
AU - Kwang-Sun LEE
AU - Sang-Il HAN
AU - Sang-Gyu PARK
AU - Soo-Ik CHAE
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2001
AB - A chip is described that integrates two multimedia VLIW processor cores with a hardware streaming engine. It can implement a real-time videophone, or an MPEG4 codec. Each processor core has identical resources, and shares the memory and system I/O interface units. With its symmetric structure, applications can be executed on either processor without constraints. To accelerate multimedia-specific applications, the architecture of this processor has several features. It merges the features of a RISC and a DSP, its instruction set is extended to accelerate both video and audio applications, and it supports an efficient embedded memory system, to reduce both the bandwidth and the latency for multimedia applications needing frequent memory accesses. The chip size will be 100 mm2 die that contains 700 K logic gates, 60 KB RAM, and 16 KB ROM, in a 0.25-µm CMOS standard cell technology. At 65 MHz operating frequency, it can process H.263 video coding at CIF 15 frames/sec, and G.723.1 audio coding with an 80% processing time allocation.
ER -