The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O transmissor e receptor óptico de 12 canais DC para 622 Mbit/s/ch foram desenvolvidos para transmissão de dados brutos paralelos de bits de alta capacidade e bastante longos (cerca de 100 m) em interconexão intra e entre gabinetes de comutação em grande escala , roteamento e sistema de computação. A transmissão de dados brutos paralelamente a bits é feita usando um circuito receptor de controle de limite de decisão automático operacional bit a bit com uma configuração acoplada a CC, os pinos-PDs com seus ânodos e cátodos separados canal por canal, e um pré-amplificador receptor com filtro passa-baixa. O transmissor consiste em uma unidade de subconjunto LD de 12 canais e um driver LD LSI. A unidade de submontagem LD consiste em uma matriz de 12 canais de LDs de heteroestrutura enterrada planar (PBH) de 1.3 µm com características de alta temperatura e fibras multimodo de índice graduado 62.5/125 (GI62.5 MMFs). Os LDs PBH de 1.3 µm e os MMFs GI62.5 são acoplados opticamente pela tecnologia de alinhamento visual passivo na ranhura Si V. O receptor consiste em uma unidade de subconjunto PD de 12 canais e um receptor LSI. A unidade de submontagem pin-PD consiste em uma matriz de 12 canais de pin-PDs e GI62.5 MMFs. Eles são acoplados opticamente usando uma ligação flip-chip na ranhura Si V. O transmissor e o receptor possuem, cada um, onze canais de dados e um canal de clock. O tamanho é tão pequeno quanto 3.6 cc para cada módulo e os consumos de energia são de 1.7 W (transmissor) e 1.35 W (receptor). Eles transmitiram dados brutos paralelos de bits através de uma fita de 100 metros de MMFs GI62.5 em uma faixa de temperatura ambiente de 0-70
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Kazunori MIYOSHI, Ichiro HATAKEYAMA, Jun'ichi SASAKI, Takahiro NAKAMURA, "12-Channel DC to 622-Mbit/s/ch Parallel Optical Transmitter and Receiver for Bit-Parallel Raw Data Transmission" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 3, pp. 304-311, March 2001, doi: .
Abstract: 12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_3_304/_p
Copiar
@ARTICLE{e84-c_3_304,
author={Kazunori MIYOSHI, Ichiro HATAKEYAMA, Jun'ichi SASAKI, Takahiro NAKAMURA, },
journal={IEICE TRANSACTIONS on Electronics},
title={12-Channel DC to 622-Mbit/s/ch Parallel Optical Transmitter and Receiver for Bit-Parallel Raw Data Transmission},
year={2001},
volume={E84-C},
number={3},
pages={304-311},
abstract={12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70
keywords={},
doi={},
ISSN={},
month={March},}
Copiar
TY - JOUR
TI - 12-Channel DC to 622-Mbit/s/ch Parallel Optical Transmitter and Receiver for Bit-Parallel Raw Data Transmission
T2 - IEICE TRANSACTIONS on Electronics
SP - 304
EP - 311
AU - Kazunori MIYOSHI
AU - Ichiro HATAKEYAMA
AU - Jun'ichi SASAKI
AU - Takahiro NAKAMURA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2001
AB - 12-channel DC to 622-Mbit/s/ch optical transmitter and receiver have been developed for high-capacity and rather long (about 100 m) bit-parallel raw data transmission in intra- and inter-cabinet interconnection of large-scale switching, routing and computing system. Bit-parallel raw data transmission is done by using a bit-by-bit operational automatic decision threshold control receiver circuit with a DC-coupled configuration, the pin-PDs with their anodes and cathodes separated in a channel-by-channel manner, and a receiver preamplifier with a low-pass filter. The transmitter consists of a 12-channel LD sub-assembly unit and a LD driver LSI. The LD sub-assembly unit consists of a 12-channel array of high temperature characteristic 1.3-µm planar buried hetero-structure (PBH) LDs and 62.5/125 graded-index multi-mode fibers (GI62.5 MMFs). The 1.3-µm PBH LDs and the GI62.5 MMFs are optically coupled by passively visual alignment technology on the Si V-groove. The receiver consists of a 12-channel pin-PD sub-assembly unit and a receiver LSI. The pin-PD sub-assembly unit consist of a 12-channel array of pin-PDs and GI62.5 MMFs. They are optically coupled by using a flip-chip bonding on the Si V-groove. The transmitter and receiver each have eleven data channels and one clock channel. The size is as small as 3.6 cc for each modules, and the power consumptions are 1.7 W (transmitter) and 1.35 W (receiver). They transmitted a bit-parallel raw data through a 100-meter ribbon of GI62.5 MMFs in an ambient temperature range of 0-70
ER -