The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um regulador de baixa corrente quiescente totalmente integrado Low Dropout (LDO) foi fabricado em uma tecnologia CMOS de 0.6 µm. É estável com capacitores de resistência em série efetiva (ESR) baixa e alta. Uma técnica de polarização de feedback dinâmico (DNFB) é usada para polarizar o amplificador de erro no LDO de modo que uma boa eficiência de corrente seja alcançada enquanto se mantém uma boa resposta transitória. Para comparar o desempenho dos reguladores LDO com e sem realimentação dinâmica, os amplificadores de erro são configurados para ter uma grande corrente de polarização (LC), uma pequena corrente de polarização (SC) e uma polarização com corrente de realimentação dinâmica usando chaves. Os resultados da medição mostram que os regulamentos de linha e carga do DNFB são 0.145%/V e 11 ppm/mA, respectivamente. Além disso, há cerca de 33% de redução no tempo de estabilização e na queda de tensão em comparação com o SC LDO quando a corrente de carga muda de 0 mA para 50 mA. A fim de reduzir a tensão de queda, um circuito de redução de queda baseado em DNFB também é projetado para reduzir a tensão limite do PMOS de saída do LDO. A redução de dropout medida é de 8.1 mV, que pode ser ainda mais reduzida por uma taxa de feedback maior no DNFB. A corrente quiescente deste LDO é medida como 59.4 µ A e este LDO pode fornecer uma corrente de saída máxima de 250 mA a uma tensão de entrada de 3.6 V. A área ativa deste LDO é 760 µ m
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Yen-Shyung SHYU, Jiin-Chuan WU, "A 60 µA Quiscent Current, 250 mA CMOS Low Dropout Regulator" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 5, pp. 693-703, May 2001, doi: .
Abstract: A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_5_693/_p
Copiar
@ARTICLE{e84-c_5_693,
author={Yen-Shyung SHYU, Jiin-Chuan WU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 60 µA Quiscent Current, 250 mA CMOS Low Dropout Regulator},
year={2001},
volume={E84-C},
number={5},
pages={693-703},
abstract={A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m
keywords={},
doi={},
ISSN={},
month={May},}
Copiar
TY - JOUR
TI - A 60 µA Quiscent Current, 250 mA CMOS Low Dropout Regulator
T2 - IEICE TRANSACTIONS on Electronics
SP - 693
EP - 703
AU - Yen-Shyung SHYU
AU - Jiin-Chuan WU
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E84-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2001
AB - A fully integrated Low Dropout (LDO), low quiescent current regulator has been fabricated in a 0.6 µm CMOS technology. It is stable with low and high effective series resistance (ESR) capacitors. A dynamic feedback (DNFB) bias technique is used to bias the error amplifier in the LDO such that good current efficiency is achieved while maintaining a good transient response. In order to compare the performance of the LDO regulators with and without dynamic feedback, the error amplifiers are configured to have a large bias current (LC), a small bias current (SC) and a bias with dynamic feedback current using switches. The measurement results show that DNFB's line and load regulations are 0.145%/V and 11 ppm/mA, respectively. Besides, there is about 33% reduction in settling time and voltage drop compared with SC LDO when load current is switching from 0 mA to 50 mA. In order to reduce the dropout voltage, a dropout reduction circuitry based on DNFB is also designed to reduce the threshold voltage of LDO's output PMOS. The measured dropout reduction is 8.1 mV which can be further reduced by a larger feedback ratio in DNFB. The quiescent current of this LDO is measured to be 59.4 µ A and this LDO can provide a maximum output current of 250 mA at an input voltage of 3.6 V. The active area of this LDO is 760 µ m
ER -