The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
O dimensionamento da tecnologia se tornará difícil devido ao power wall. Por outro lado, a futura tecnologia informática e de comunicações exigirá uma redução adicional na dissipação de energia. Como nenhuma nova tecnologia de dispositivo energeticamente eficiente está no horizonte, o design CMOS de baixo consumo de energia deve ser desafiado. Este artigo discute o que e quanto os projetistas podem fazer para reduzir o consumo de energia do CMOS.
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Tadahiro KURODA, "Low Power CMOS Design Challenges" in IEICE TRANSACTIONS on Electronics,
vol. E84-C, no. 8, pp. 1021-1028, August 2001, doi: .
Abstract: Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e84-c_8_1021/_p
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@ARTICLE{e84-c_8_1021,
author={Tadahiro KURODA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Power CMOS Design Challenges},
year={2001},
volume={E84-C},
number={8},
pages={1021-1028},
abstract={Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - Low Power CMOS Design Challenges
T2 - IEICE TRANSACTIONS on Electronics
SP - 1021
EP - 1028
AU - Tadahiro KURODA
PY - 2001
DO -
JO - IEICE TRANSACTIONS on Electronics
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VL - E84-C
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JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2001
AB - Technology scaling will become difficult due to power wall. On the other hand, future computer and communications technology will require further reduction in power dissipation. Since no new energy efficient device technology is on the horizon, low power CMOS design should be challenged. This paper discusses what and how much designers can do for CMOS power reduction.
ER -