The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe violação construtiva de temporização (CTV) e avalia seu potencial. Ele pode ser utilizado tanto para aumentar a frequência do clock quanto para reduzir o consumo de energia. Aumentar a frequência do clock acima daquela determinada pelos caminhos críticos causa violações de temporização. Por outro lado, embora a redução da tensão de alimentação possa resultar em economias substanciais de energia, ela também causa maior atraso na porta e, portanto, o relógio deve ser lento para não violar as restrições de tempo dos caminhos críticos. Contudo, se forem fornecidos quaisquer mecanismos de tolerância para as violações de temporização, não é necessário manter as restrições. Em vez disso, as violações seriam construtivas para altas frequências de clock ou para economia de energia. A partir destas observações, propomos o CTV, que é apoiado no mecanismo tolerante baseado em mecanismos contemporâneos de execução especulativa. Avaliamos o CTV utilizando um simulador ciclo a ciclo e apresentamos seu potencial consideravelmente promissor.
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Toshinori SATO, Itsujiro ARITA, "Potential of Constructive Timing-Violation" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 2, pp. 323-330, February 2002, doi: .
Abstract: This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_2_323/_p
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@ARTICLE{e85-c_2_323,
author={Toshinori SATO, Itsujiro ARITA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Potential of Constructive Timing-Violation},
year={2002},
volume={E85-C},
number={2},
pages={323-330},
abstract={This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.},
keywords={},
doi={},
ISSN={},
month={February},}
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TY - JOUR
TI - Potential of Constructive Timing-Violation
T2 - IEICE TRANSACTIONS on Electronics
SP - 323
EP - 330
AU - Toshinori SATO
AU - Itsujiro ARITA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 2
JA - IEICE TRANSACTIONS on Electronics
Y1 - February 2002
AB - This paper proposes constructive timing-violation (CTV) and evaluates its potential. It can be utilized both for increasing clock frequency and for reducing energy consumption. Increasing clock frequency over that determined by the critical paths causes timing violations. On the other hand, while supply voltage reduction can result in substantial power savings, it also causes larger gate delay and thus clock must be slow down in order not to violate timing constraints of critical paths. However, if any tolerant mechanisms are provided for the timing violations, it is not necessary to keep the constraints. Rather, the violations would be constructive for high clock frequency or for energy savings. From these observations, we propose the CTV, which is supported by the tolerant mechanism based on contemporary speculative execution mechanisms. We evaluate the CTV using a cycle-by-cycle simulator and present its considerably promising potential.
ER -