The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo são apresentadas características de um sistema digital dedicado à rápida execução do algoritmo FDTD, amplamente utilizado para simulação eletromagnética. Tal sistema é concebido como um módulo que se comunica com um computador pessoal host através de um barramento PCI, e é baseado em um VLSI ASIC, que implementa o mecanismo de “atualização de campo”. A estrutura do sistema é definida por meio de uma linguagem de descrição de hardware, permitindo manter a especificação do sistema de alto nível independente da tecnologia de fabricação real. Foi realizada uma implementação virtual do sistema, mapeando tal descrição em um estilo de célula padrão em uma tecnologia comercial de 0.35 µm. Simulações mostram que uma aceleração significativa pode ser alcançada em relação às implementações de software de última geração do mesmo algoritmo.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Pisana PLACIDI, Leonardo VERDUCCI, Guido MATRELLA, Luca ROSELLI, Paolo CIAMPOLINI, "A Custom VLSI Architecture for the Solution of FDTD Equations" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 3, pp. 572-577, March 2002, doi: .
Abstract: In this paper, characteristics of a digital system dedicated to the fast execution of the FDTD algorithm, widely used for electromagnetic simulation, are presented. Such system is conceived as a module communicating with a host personal computer via a PCI bus, and is based on a VLSI ASIC, which implements the "field-update" engine. The system structure is defined by means of a hardware description language, allowing to keep high-level system specification independent of the actual fabrication technology. A virtual implementation of the system has been carried out, by mapping such description in a standard-cell style on a commercial 0.35 µm technology. Simulations show that significant speed-up can be achieved, with respect to state-of-the-art software implementations of the same algorithm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_3_572/_p
Copiar
@ARTICLE{e85-c_3_572,
author={Pisana PLACIDI, Leonardo VERDUCCI, Guido MATRELLA, Luca ROSELLI, Paolo CIAMPOLINI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Custom VLSI Architecture for the Solution of FDTD Equations},
year={2002},
volume={E85-C},
number={3},
pages={572-577},
abstract={In this paper, characteristics of a digital system dedicated to the fast execution of the FDTD algorithm, widely used for electromagnetic simulation, are presented. Such system is conceived as a module communicating with a host personal computer via a PCI bus, and is based on a VLSI ASIC, which implements the "field-update" engine. The system structure is defined by means of a hardware description language, allowing to keep high-level system specification independent of the actual fabrication technology. A virtual implementation of the system has been carried out, by mapping such description in a standard-cell style on a commercial 0.35 µm technology. Simulations show that significant speed-up can be achieved, with respect to state-of-the-art software implementations of the same algorithm.},
keywords={},
doi={},
ISSN={},
month={March},}
Copiar
TY - JOUR
TI - A Custom VLSI Architecture for the Solution of FDTD Equations
T2 - IEICE TRANSACTIONS on Electronics
SP - 572
EP - 577
AU - Pisana PLACIDI
AU - Leonardo VERDUCCI
AU - Guido MATRELLA
AU - Luca ROSELLI
AU - Paolo CIAMPOLINI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2002
AB - In this paper, characteristics of a digital system dedicated to the fast execution of the FDTD algorithm, widely used for electromagnetic simulation, are presented. Such system is conceived as a module communicating with a host personal computer via a PCI bus, and is based on a VLSI ASIC, which implements the "field-update" engine. The system structure is defined by means of a hardware description language, allowing to keep high-level system specification independent of the actual fabrication technology. A virtual implementation of the system has been carried out, by mapping such description in a standard-cell style on a commercial 0.35 µm technology. Simulations show that significant speed-up can be achieved, with respect to state-of-the-art software implementations of the same algorithm.
ER -