The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Apresentamos uma estrutura de design de um servidor topo de linha baseado em tecnologias de circuito Single-Flux-Quantum (SFQ). O servidor aqui proposto possui múltiplos microprocessadores e memórias, que são montados em uma única placa ou pacote e são conectados entre si por chaves de interconexão SFQ. A largura de banda extremamente grande de até 100 Gbps/canal na interconexão será realizada devido à natureza de alto rendimento dos circuitos SFQ. Memórias SFQ ou memórias híbridas Josephson-CMOS são empregadas como memória compartilhada do multiprocessador. Os microprocessadores SFQ são construídos com base na arquitetura de complexidade reduzida (CORE), na qual a complexidade do sistema é facilitada em troca do uso de uma alta taxa de clock dos circuitos SFQ. O processador é o chamado processador Java que executa diretamente os códigos de bytes Java. Assumindo um avanço adequado do Nb/AlOx/Nb tecnologia de processo de circuito integrado, estimamos que o consumo de energia do sistema de servidor incluindo um criocooler é reduzido por um fator de vinte em comparação com o futuro sistema CMOS com o mesmo desempenho de processador, enquanto o sistema SFQ tem 100 vezes de magnitude maior largura de banda do processador de memória.
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Akira FUJIMAKI, Yoshiaki TAKAI, Nobuyuki YOSHIKAWA, "High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 3, pp. 612-616, March 2002, doi: .
Abstract: We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_3_612/_p
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@ARTICLE{e85-c_3_612,
author={Akira FUJIMAKI, Yoshiaki TAKAI, Nobuyuki YOSHIKAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology},
year={2002},
volume={E85-C},
number={3},
pages={612-616},
abstract={We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - High-End Server Based on Complexity-Reduced Architecture for Superconductor Technology
T2 - IEICE TRANSACTIONS on Electronics
SP - 612
EP - 616
AU - Akira FUJIMAKI
AU - Yoshiaki TAKAI
AU - Nobuyuki YOSHIKAWA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 3
JA - IEICE TRANSACTIONS on Electronics
Y1 - March 2002
AB - We present a design framework of a high-end server based on Single-Flux-Quantum (SFQ) circuit technologies. The server proposed here has multiple microprocessors and memories, which are mounted on a single board or package and are connected each other by SFQ interconnection switches. The extremely large bandwidth up to 100 Gbps/channel in the interconnection will be realized because of high throughput nature of the SFQ circuits. SFQ memories or Josephson-CMOS hybrid memories are employed as the shared memory of the multiprocessor. The SFQ microprocessors are constructed based on the complexity-reduced (CORE) architecture, in which complexity of the system is eased in exchange for using a high clock rate of the SFQ circuits. The processor is so-called Java-processor that directly executes the Java Byte Codes. Assuming a proper advancement of the Nb/AlOx/Nb integrated circuit process technology, we have estimated that the power consumption of the server system including a cryocooler is reduced by a factor of twenty as compared to the future CMOS system with the same processor performance, while the SFQ system has 100 times of magnitude larger memory-processor bandwidth.
ER -