The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo aborda os desafios fundamentais e possíveis soluções no projeto e fabricação de transistores CMOS em escala nanométrica. Componentes tecnológicos essenciais, como dielétricos de porta avançados, junção ultra-rasa, engenharia de perfil de dopante de canal e salicida são discutidos. O transistor ultraescalado com comprimento de porta física de até 15 nm é demonstrado como um esforço contínuo para levar a tecnologia CMOS planar tradicional ao seu limite físico.
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Bin YU, "CMOS Transistor in Nanoscale Era" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 5, pp. 1052-1056, May 2002, doi: .
Abstract: This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1052/_p
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@ARTICLE{e85-c_5_1052,
author={Bin YU, },
journal={IEICE TRANSACTIONS on Electronics},
title={CMOS Transistor in Nanoscale Era},
year={2002},
volume={E85-C},
number={5},
pages={1052-1056},
abstract={This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - CMOS Transistor in Nanoscale Era
T2 - IEICE TRANSACTIONS on Electronics
SP - 1052
EP - 1056
AU - Bin YU
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - This paper addresses the fundamental challenges and possible solutions in designing and fabricating nanometer-scale CMOS transistor. Essential technology components such as advanced gate dielectrics, ultra-shallow junction, channel dopant profile engineering, and salicide are discussed. Ultra-scaled transistor with physical gate length down to 15 nm is demonstrated as a continued effort to push the traditional planar CMOS technology towards its physical limit.
ER -