The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Uma nova porta de transferência de valores múltiplos (porta T) consistindo de transistores de túnel de superfície de múltiplas junções (MJSTTs) e FETs de heterojunção (HJFETs) foi desenvolvida e sua operação foi confirmada por simulação e experimento. O número de dispositivos necessários para formar a porta T pode ser drasticamente reduzido devido à alta funcionalidade do MJSTT; ou seja, apenas três MJSTTs e três HJFETs são necessários para fabricar a porta T de três valores. Esse número de transistores é menos da metade de um circuito convencional. O circuito fabricado exibiu uma operação básica de porta T com várias funções lógicas. Além disso, apenas uma porta T é necessária para formar um circuito D-flip-flop (D-FF) de valores múltiplos.
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Tetsuya UEMURA, Toshio BABA, "Multiple-Valued T-Gate Based on Multiple Junction Surface Tunnel Transistor" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 7, pp. 1486-1490, July 2002, doi: .
Abstract: A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_7_1486/_p
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@ARTICLE{e85-c_7_1486,
author={Tetsuya UEMURA, Toshio BABA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Multiple-Valued T-Gate Based on Multiple Junction Surface Tunnel Transistor},
year={2002},
volume={E85-C},
number={7},
pages={1486-1490},
abstract={A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.},
keywords={},
doi={},
ISSN={},
month={July},}
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TY - JOUR
TI - Multiple-Valued T-Gate Based on Multiple Junction Surface Tunnel Transistor
T2 - IEICE TRANSACTIONS on Electronics
SP - 1486
EP - 1490
AU - Tetsuya UEMURA
AU - Toshio BABA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2002
AB - A novel multiple-valued transfer gate (T-gate) consisting of multiple-junction surface tunnel transistors (MJSTTs) and hetero-junction FETs (HJFETs) was developed and its operation was confirmed by both simulation and experiment. The number of the devices required to form the T-gate can be drastically reduced because of the high functionality of the MJSTT; namely only three MJSTTs and three HJFETs are required to fabricate the three-valued T-gate. This number of transistors is less than half that of a conventional circuit. The fabricated circuit exhibited a basic T-gate operation with various logic functions. Furthermore, only one T-gate is needed to form a multiple-valued D-flip-flop (D-FF) circuit.
ER -