The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, é proposto um conversor analógico-digital de dobramento/interpolação CMOS de 3 V e 8 bits 200MSPS. Ele emprega uma arquitetura eficiente cuja FR (Folding Rate) é 8, NFB (Number of Folding Block) é 4 e IR (Interpolating Rate) é 8. Com o propósito de melhorar o SNR, circuitos distribuídos de rastreamento e retenção são incluídos na frente final do estágio de entrada. Para obter uma operação de alta velocidade e baixa potência, é proposta uma trava analógica dinâmica melhorada. Além disso, é proposto um codificador digital baseado em um novo algoritmo de termômetro e um algoritmo de correção de erros de atraso. O chip foi fabricado com tecnologia CMOS de n poços de 0.35 µm, 2 poli e 3 metais. A área efetiva do chip é 1200 µm
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Sanghoon JOO, Minkyu SONG, "A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 8, pp. 1554-1561, August 2002, doi: .
Abstract: In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_8_1554/_p
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@ARTICLE{e85-c_8_1554,
author={Sanghoon JOO, Minkyu SONG, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder},
year={2002},
volume={E85-C},
number={8},
pages={1554-1561},
abstract={In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A 3V 8-Bit 200MSPS CMOS ADC with an Improved Analog Latch and a Novel Digital Encoder
T2 - IEICE TRANSACTIONS on Electronics
SP - 1554
EP - 1561
AU - Sanghoon JOO
AU - Minkyu SONG
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2002
AB - In this paper, a 3 V 8-bit 200MSPS CMOS folding/interpolation Analog-to-Digital Converter is proposed. It employs an efficient architecture whose FR (Folding Rate) is 8, NFB (Number of Folding Block) is 4, and IR (Interpolating Rate) is 8. For the purpose of improving SNR, distributed track and hold circuits are included at the front end of input stage. In order to obtain a high speed and low power operation, an improved dynamic analog latch is proposed. Further, a digital encoder based on a novel thermometer algorithm and a delay error correction algorithm is proposed. The chip has been fabricated with a 0.35 µm 2-poly 3-metal n-well CMOS technology. The effective chip area is 1200 µm
ER -