The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É descrita uma técnica de calibração digital, que corrige erros devido à incompatibilidade de capacitores no ADC em pipeline e mede diretamente os coeficientes de erro usando o gráfico ADC INL. A técnica proposta pode ser aplicada a vários tipos de arquiteturas ADC em pipeline. Os resultados dos testes usando um ADC em pipeline de 10 bits implementado mostram que o ADC atinge uma relação sinal-ruído e distorção de pico de 56.5 dB, uma não linearidade integral de pico de 0.3 LSB e uma não linearidade diferencial de pico de 0.3 LSB usando a calibração digital.
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Masanori FURUTA, Shoji KAWAHITO, Daisuke MIYAZAKI, "A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters" in IEICE TRANSACTIONS on Electronics,
vol. E85-C, no. 8, pp. 1562-1568, August 2002, doi: .
Abstract: A digital calibration technique, which corrects errors due to capacitor mismatch in pipelined ADC and directly measures the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 56.5 dB, a peak integral non-linearity of 0.3 LSB, and a peak differential non-linearity of 0.3 LSB using the digital calibration.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_8_1562/_p
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@ARTICLE{e85-c_8_1562,
author={Masanori FURUTA, Shoji KAWAHITO, Daisuke MIYAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters},
year={2002},
volume={E85-C},
number={8},
pages={1562-1568},
abstract={A digital calibration technique, which corrects errors due to capacitor mismatch in pipelined ADC and directly measures the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 56.5 dB, a peak integral non-linearity of 0.3 LSB, and a peak differential non-linearity of 0.3 LSB using the digital calibration.},
keywords={},
doi={},
ISSN={},
month={August},}
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TY - JOUR
TI - A Digital Calibration Technique of Capacitor Mismatch for Pipelined Analog-to-Digital Converters
T2 - IEICE TRANSACTIONS on Electronics
SP - 1562
EP - 1568
AU - Masanori FURUTA
AU - Shoji KAWAHITO
AU - Daisuke MIYAZAKI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2002
AB - A digital calibration technique, which corrects errors due to capacitor mismatch in pipelined ADC and directly measures the error coefficients using the ADC INL plot, is described. The proposed technique can be applied for various types of pipelined ADC architectures. Test results using an implemented 10-bit pipelined ADC show that the ADC achieves a peak signal-to-noise-and-distortion ratio of 56.5 dB, a peak integral non-linearity of 0.3 LSB, and a peak differential non-linearity of 0.3 LSB using the digital calibration.
ER -