The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este relatório concentra-se em um esquema de otimização de MOSFETs avançados para projetar circuitos CMOS com alta eficiência energética. Para este propósito, o modelo compacto baseado em física HiSIM2 é aplicado para que a relação entre as características do dispositivo e do circuito possa ser investigada adequadamente. É demonstrado que o efeito de canal curto, que geralmente é medido pela mudança de tensão limite em relação aos MOSFETs de canal longo, fornece uma medida consistente para a degradação do desempenho do dispositivo com comprimento de canal reduzido. No entanto, as degradações de desempenho dos circuitos CMOS, como a perda de energia, não podem ser previstas apenas pela mudança de tensão limite. Aqui, a oscilação subliminar é identificada como uma medida adicional importante para o projeto de circuitos CMOS com eficiência energética. O aumento da oscilação sublimiar torna-se óbvio quando a mudança da tensão limite é maior que 0.15V.
Arnab MUKHOPADHYAY
Hiroshima University,Indian Institute of Engineering Science and Technology
Tapas Kumar MAITI
Hiroshima University
Sandip BHATTACHARYA
Hiroshima University
Takahiro IIZUKA
Hiroshima University
Hideyuki KIKUCHIHARA
Hiroshima University
Mitiko MIURA-MATTAUSCH
Hiroshima University
Hafizur RAHAMAN
Indian Institute of Engineering Science and Technology
Sadayuki YOSHITOMI
Toshiba Memory Corporation
Dondee NAVARRO
Hiroshima University
Hans Jürgen MATTAUSCH
Hiroshima University
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Arnab MUKHOPADHYAY, Tapas Kumar MAITI, Sandip BHATTACHARYA, Takahiro IIZUKA, Hideyuki KIKUCHIHARA, Mitiko MIURA-MATTAUSCH, Hafizur RAHAMAN, Sadayuki YOSHITOMI, Dondee NAVARRO, Hans Jürgen MATTAUSCH, "Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 6, pp. 487-494, June 2019, doi: 10.1587/transele.2018ECP5046.
Abstract: This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018ECP5046/_p
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@ARTICLE{e102-c_6_487,
author={Arnab MUKHOPADHYAY, Tapas Kumar MAITI, Sandip BHATTACHARYA, Takahiro IIZUKA, Hideyuki KIKUCHIHARA, Mitiko MIURA-MATTAUSCH, Hafizur RAHAMAN, Sadayuki YOSHITOMI, Dondee NAVARRO, Hans Jürgen MATTAUSCH, },
journal={IEICE TRANSACTIONS on Electronics},
title={Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs},
year={2019},
volume={E102-C},
number={6},
pages={487-494},
abstract={This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.},
keywords={},
doi={10.1587/transele.2018ECP5046},
ISSN={1745-1353},
month={June},}
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TY - JOUR
TI - Prevention of Highly Power-Efficient Circuits due to Short-Channel Effects in MOSFETs
T2 - IEICE TRANSACTIONS on Electronics
SP - 487
EP - 494
AU - Arnab MUKHOPADHYAY
AU - Tapas Kumar MAITI
AU - Sandip BHATTACHARYA
AU - Takahiro IIZUKA
AU - Hideyuki KIKUCHIHARA
AU - Mitiko MIURA-MATTAUSCH
AU - Hafizur RAHAMAN
AU - Sadayuki YOSHITOMI
AU - Dondee NAVARRO
AU - Hans Jürgen MATTAUSCH
PY - 2019
DO - 10.1587/transele.2018ECP5046
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2019
AB - This report focuses on an optimization scheme of advanced MOSFETs for designing CMOS circuits with high power efficiency. For this purpose the physics-based compact model HiSIM2 is applied so that the relationship between device and circuit characteristics can be investigated properly. It is demonstrated that the short-channel effect, which is usually measured by the threshold-voltage shift relative to long-channel MOSFETs, provides a consistent measure for device-performance degradation with reduced channel length. However, performance degradations of CMOS circuits such as the power loss cannot be predicted by the threshold-voltage shift alone. Here, the subthreshold swing is identified as an additional important measure for power-efficient CMOS circuit design. The increase of the subthreshold swing is verified to become obvious when the threshold-voltage shift is larger than 0.15V.
ER -