The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um novo flip-flop baseado em amplificador sensor de baixa potência (FF) é apresentado. Ao usar um projeto simplificado de trava baseado em SRAM e um esquema de circuito lógico de transistor de passagem (PTL), a contagem de transistores do projeto FF é bastante reduzida, bem como o desempenho de potência de vazamento. As reivindicações de desempenho são verificadas através de extensas simulações pós-layout. Comparado ao projeto FF do amplificador sensor convencional, o circuito proposto atinge 19.6% de redução de vazamento. Além disso, o atraso e a área são reduzidos em 21.8% e 31%, respectivamente. A vantagem de desempenho torna-se ainda melhor quando o flip-flop é integrado Narquivo de registro de -bit.
Po-Yu KUO
National Yunlin University of Science & Technology
Chia-Hsin HSIEH
National Yunlin University of Science & Technology
Jin-Fa LIN
Chaoyang University of Technology
Ming-Hwa SHEU
National Yunlin University of Science & Technology
Yi-Ting HUNG
National Yunlin University of Science & Technology
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Po-Yu KUO, Chia-Hsin HSIEH, Jin-Fa LIN, Ming-Hwa SHEU, Yi-Ting HUNG, "Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 11, pp. 833-838, November 2019, doi: 10.1587/transele.2018ECP5059.
Abstract: A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018ECP5059/_p
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@ARTICLE{e102-c_11_833,
author={Po-Yu KUO, Chia-Hsin HSIEH, Jin-Fa LIN, Ming-Hwa SHEU, Yi-Ting HUNG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design},
year={2019},
volume={E102-C},
number={11},
pages={833-838},
abstract={A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.},
keywords={},
doi={10.1587/transele.2018ECP5059},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - Low Complexity and Low Power Sense-Amplifier Based Flip-Flop Design
T2 - IEICE TRANSACTIONS on Electronics
SP - 833
EP - 838
AU - Po-Yu KUO
AU - Chia-Hsin HSIEH
AU - Jin-Fa LIN
AU - Ming-Hwa SHEU
AU - Yi-Ting HUNG
PY - 2019
DO - 10.1587/transele.2018ECP5059
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2019
AB - A novel low power sense-amplifier based flip-flop (FF) is presented. By using a simplified SRAM based latch design and pass transistor logic (PTL) circuit scheme, the transistor-count of the FF design is greatly reduced as well as leakage power performance. The performance claims are verified through extensive post-layout simulations. Compared to the conventional sense-amplifier FF design, the proposed circuit achieves 19.6% leakage reduction. Moreover, the delay, and area are reduced by 21.8% and 31%, respectively. The performance edge becomes even better when the flip-flop is integrated in N-bit register file.
ER -