The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, um novo sistema transceptor para o sistema de comunicação no veículo é proposto para melhorar a taxa de transmissão de dados e a precisão do tempo em aplicações baseadas em TDM. O sistema proposto utiliza canal ponto a ponto (P2P), um caminho de encaminhamento de relógio de circuito fechado e um transceptor com repetidor e ajustador de atraso de relógio. O sistema proposto com 4 nós ECU (Unidade de Computação Eletrônica) é implementado em tecnologia CMOS de 180 nm e, quando comparado com o sistema convencional baseado em barramento, alcançou transmissão de dados 125 vezes mais rápida. A taxa de dados máxima foi de 2.5 Gbps com fonte de alimentação de 1.8 V e o pior jitter pico a pico para os sinais de dados e clock acima de 5000 símbolos de dados foi de cerca de 49.6 ps e 9.8 ps, respectivamente.
Kyongsu LEE
Pohang University of Science and Technology (POSTECH)
Jae-Yoon SIM
Pohang University of Science and Technology (POSTECH)
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Kyongsu LEE, Jae-Yoon SIM, "A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System" in IEICE TRANSACTIONS on Electronics,
vol. E102-C, no. 10, pp. 766-769, October 2019, doi: 10.1587/transele.2018ECS6023.
Abstract: In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2018ECS6023/_p
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@ARTICLE{e102-c_10_766,
author={Kyongsu LEE, Jae-Yoon SIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System},
year={2019},
volume={E102-C},
number={10},
pages={766-769},
abstract={In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.},
keywords={},
doi={10.1587/transele.2018ECS6023},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - A 2.5Gbps Transceiver and Channel Architecture for High-Speed Automotive Communication System
T2 - IEICE TRANSACTIONS on Electronics
SP - 766
EP - 769
AU - Kyongsu LEE
AU - Jae-Yoon SIM
PY - 2019
DO - 10.1587/transele.2018ECS6023
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E102-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2019
AB - In this paper, a new transceiver system for the in-vehicle communication system is proposed to enhance data transmission rate and timing accuracy in TDM-based application. The proposed system utilizes point-to-point (P2P) channel, a closed-loop clock forwarding path, and a transceiver with a repeater and clock delay adjuster. The proposed system with 4 ECU (Electronic Computing Unit) nodes is implemented in 180nm CMOS technology and, when compared with conventional bus-based system, achieved more than 125 times faster data transmission. The maximum data rate was 2.5Gbps at 1.8V power supply and the worst peak-to-peak jitter for the data and clock signals over 5000 data symbols were about 49.6ps and 9.8ps respectively.
ER -