The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um IC amplificador de potência (PA) empilhado altamente linear com banda de 28 GHz. Uma estrutura FET de 4 pilhas é empregada para alta potência de saída, considerando a baixa tensão de ruptura dos transistores MOSFET escalonados. Um novo circuito de polarização adaptativo é proposto para controlar dinamicamente a tensão de polarização porta-fonte para MOSFETs de amplificação. O novo viés adaptativo permite que o PA atinja alta linearidade com alta eficiência de recuo. Além disso, a distorção de intermodulação de terceira ordem (IM3) é melhorada por uma estrutura multi-cascode. O PA IC foi projetado, fabricado e totalmente testado em tecnologia SOI CMOS de 56 nm. Com uma tensão de alimentação de 4 V, o PA IC alcançou uma potência de saída de 20.0 dBm com um PAE de até 38.1% no ponto de compressão de ganho de 1 dB (P1dB). Além disso, os PAEs com recuo de 3 dB e 6 dB de P1dB são de 36.2% e 28.7%, respectivamente. O PA IC exibe um ponto de interceptação de terceira ordem de saída (OIP3) de 25.0 dBm.
Cuilin CHEN
Waseda University
Tsuyoshi SUGIURA
Samsung R&D Institute Japan
Toshihiko YOSHIMASU
Waseda University
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Cuilin CHEN, Tsuyoshi SUGIURA, Toshihiko YOSHIMASU, "A 28-GHz-Band Highly Linear Stacked-FET Power Amplifier IC with High Back-Off PAE in 56-nm SOI CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 4, pp. 153-160, April 2020, doi: 10.1587/transele.2019CDP0003.
Abstract: This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019CDP0003/_p
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@ARTICLE{e103-c_4_153,
author={Cuilin CHEN, Tsuyoshi SUGIURA, Toshihiko YOSHIMASU, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 28-GHz-Band Highly Linear Stacked-FET Power Amplifier IC with High Back-Off PAE in 56-nm SOI CMOS},
year={2020},
volume={E103-C},
number={4},
pages={153-160},
abstract={This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.},
keywords={},
doi={10.1587/transele.2019CDP0003},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A 28-GHz-Band Highly Linear Stacked-FET Power Amplifier IC with High Back-Off PAE in 56-nm SOI CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 153
EP - 160
AU - Cuilin CHEN
AU - Tsuyoshi SUGIURA
AU - Toshihiko YOSHIMASU
PY - 2020
DO - 10.1587/transele.2019CDP0003
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2020
AB - This paper presents a 28-GHz-band highly linear stacked-FET power amplifier (PA) IC. A 4-stacked-FET structure is employed for high output power considering the low breakdown voltage of scaled MOSFET transistors. A novel adaptive bias circuit is proposed to dynamically control the gate-to-source bias voltage for amplification MOSFETs. The novel adaptive bias allows the PA to attain high linearity with high back-off efficiency. In addition, the third-order intermodulation distortion (IM3) is improved by a multi-cascode structure. The PA IC is designed, fabricated and fully tested in 56-nm SOI CMOS technology. At a supply voltage of 4 V, the PA IC has achieved an output power of 20.0 dBm with a PAE as high as 38.1% at the 1-dB gain compression point (P1dB). Moreover, PAEs at 3-dB and 6-dB back-off from P1dB are 36.2% and 28.7%, respectively. The PA IC exhibits an output third-order intercept point (OIP3) of 25.0 dBm.
ER -