The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Nos últimos anos, a rede neural profunda (DNN) alcançou resultados consideráveis em muitas tarefas de inteligência artificial, por exemplo, processamento de linguagem natural. No entanto, a complexidade computacional da DNN é extremamente alta. Além disso, o desempenho da arquitetura de computação tradicional de von Neumann tem diminuído devido ao problema da parede de memória. O processamento na memória (PIM), que coloca a computação na memória e reduz a movimentação de dados, quebra a barreira da memória. Acredita-se que ReRAM PIM seja uma arquitetura disponível para aceleradores DNN. Neste trabalho, um novo projeto de sistema neuromórfico ReRAM é proposto para processar DNN totalmente em array de forma eficiente. A matriz ReRAM binária é composta por células de armazenamento 2T2R e amplificadores de detecção de espelho de corrente. Um esquema de referência BL fictício é proposto para geração de tensão de referência. Um modelo binário DNN (BDNN) é então construído e otimizado no conjunto de dados MNIST. O modelo atinge uma precisão de validação de 96.33% e é implantado no sistema ReRAM PIM. O método de otimização do modelo de co-projeto entre o dispositivo de hardware e o algoritmo de software é proposto com a ideia de utilizar informações de variação de hardware como incerteza no procedimento de otimização. Este método é analisado para obter um projeto de hardware viável e um modelo generalizável. Implantado com esse modelo de co-design, o array ReRAM processa DNN com alta robustez contra flutuações de fabricação.
Yue GUAN
Waseda University
Takashi OHSAWA
Waseda University
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Yue GUAN, Takashi OHSAWA, "Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm" in IEICE TRANSACTIONS on Electronics,
vol. E103-C, no. 11, pp. 685-692, November 2020, doi: 10.1587/transele.2019ECP5046.
Abstract: In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2019ECP5046/_p
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@ARTICLE{e103-c_11_685,
author={Yue GUAN, Takashi OHSAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm},
year={2020},
volume={E103-C},
number={11},
pages={685-692},
abstract={In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.},
keywords={},
doi={10.1587/transele.2019ECP5046},
ISSN={1745-1353},
month={November},}
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TY - JOUR
TI - Co-Design of Binary Processing in Memory ReRAM Array and DNN Model Optimization Algorithm
T2 - IEICE TRANSACTIONS on Electronics
SP - 685
EP - 692
AU - Yue GUAN
AU - Takashi OHSAWA
PY - 2020
DO - 10.1587/transele.2019ECP5046
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E103-C
IS - 11
JA - IEICE TRANSACTIONS on Electronics
Y1 - November 2020
AB - In recent years, deep neural network (DNN) has achieved considerable results on many artificial intelligence tasks, e.g. natural language processing. However, the computation complexity of DNN is extremely high. Furthermore, the performance of traditional von Neumann computing architecture has been slowing down due to the memory wall problem. Processing in memory (PIM), which places computation within memory and reduces the data movement, breaks the memory wall. ReRAM PIM is thought to be a available architecture for DNN accelerators. In this work, a novel design of ReRAM neuromorphic system is proposed to process DNN fully in array efficiently. The binary ReRAM array is composed of 2T2R storage cells and current mirror sense amplifiers. A dummy BL reference scheme is proposed for reference voltage generation. A binary DNN (BDNN) model is then constructed and optimized on MNIST dataset. The model reaches a validation accuracy of 96.33% and is deployed to the ReRAM PIM system. Co-design model optimization method between hardware device and software algorithm is proposed with the idea of utilizing hardware variance information as uncertainness in optimization procedure. This method is analyzed to achieve feasible hardware design and generalizable model. Deployed with such co-design model, ReRAM array processes DNN with high robustness against fabrication fluctuation.
ER -