The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma sinalização modulada por largura de pulso (PWM)[1] para enviar relógio e dados através de um par de canais para uma rede veicular onde uma cadeia fechada de interconexão ponto a ponto (P2P) entre unidades de controle eletrônico (ECU ) foi estabelecido. Para melhorar a velocidade de detecção e a margem do receptor proposto, também propusemos um novo esquema de clock e recuperação de dados (CDR) com faixa de sintonia de intervalo de unidade (UI) de 0.5 e um gerador PWM utilizando 10 fases igualmente espaçadas. A viabilidade do sistema proposto foi comprovada pela detecção bem-sucedida de dados de 1.25 Gb/s entregues através de 3 ECUs e intercanais em tecnologia CMOS de 180 nm. Comparado ao estudo anterior, o sistema proposto alcançou melhor eficiência em termos de potência, custo e confiabilidade.
Kyongsu LEE
Pohang University of Science and Technology (POSTECH)
Jae-Yoon SIM
Pohang University of Science and Technology (POSTECH)
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Kyongsu LEE, Jae-Yoon SIM, "A High-Speed PWM-Modulated Transceiver Network for Closed-Loop Channel Topology" in IEICE TRANSACTIONS on Electronics,
vol. E104-C, no. 7, pp. 350-354, July 2021, doi: 10.1587/transele.2020CDS0001.
Abstract: This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2020CDS0001/_p
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@ARTICLE{e104-c_7_350,
author={Kyongsu LEE, Jae-Yoon SIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={A High-Speed PWM-Modulated Transceiver Network for Closed-Loop Channel Topology},
year={2021},
volume={E104-C},
number={7},
pages={350-354},
abstract={This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.},
keywords={},
doi={10.1587/transele.2020CDS0001},
ISSN={1745-1353},
month={July},}
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TY - JOUR
TI - A High-Speed PWM-Modulated Transceiver Network for Closed-Loop Channel Topology
T2 - IEICE TRANSACTIONS on Electronics
SP - 350
EP - 354
AU - Kyongsu LEE
AU - Jae-Yoon SIM
PY - 2021
DO - 10.1587/transele.2020CDS0001
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E104-C
IS - 7
JA - IEICE TRANSACTIONS on Electronics
Y1 - July 2021
AB - This paper proposes a pulse-width modulated (PWM) signaling[1] to send clock and data over a pair of channels for in-vehicle network where a closed chain of point-to-point (P2P) interconnection between electronic control units (ECU) has been established. To improve detection speed and margin of proposed receiver, we also proposed a novel clock and data recovery (CDR) scheme with 0.5 unit-interval (UI) tuning range and a PWM generator utilizing 10 equally-spaced phases. The feasibility of proposed system has been proved by successfully detecting 1.25 Gb/s data delivered via 3 ECUs and inter-channels in 180 nm CMOS technology. Compared to previous study, the proposed system achieved better efficiency in terms of power, cost, and reliability.
ER -