The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
A complexidade e a escala das Networks-on-Chip (NoCs) estão crescendo à medida que mais elementos de processamento e dispositivos de memória são implementados em chips. No entanto, sob orçamentos de energia rigorosos, também é fundamental reduzir o consumo de energia das NoCs em prol da eficiência energética. Neste artigo, apresentamos três novos projetos de unidades de entrada para roteadores on-chip que tentam reduzir seu consumo de energia e, ao mesmo tempo, conservar o desempenho da rede. A ideia principal por trás de nossos projetos é organizar buffers nas unidades de entrada tendo em mente as características do tráfego da rede; como em nossas observações, apenas uma pequena parcela do tráfego de rede são pacotes longos (compostos por múltiplos flits), o que significa que é justo implementar buffers híbridos, assimétricos e reconfiguráveis para que eles sejam direcionados principalmente para pacotes curtos (tendo apenas um single flit), daí o menor consumo de energia e sobrecarga de área. As avaliações mostram que nossos projetos de unidades de entrada híbridas, assimétricas e reconfiguráveis podem alcançar uma redução média do consumo de energia por flit em 45%, 52.3% e 56.2% abaixo de 93.6% (para projetos híbridos) e 66.3% (para projetos assimétricos e reconfiguráveis) de a área original do roteador, respectivamente. Entretanto, observamos apenas uma pequena degradação na latência da rede (variando de 18.4% a 1.5%, em média) com as nossas propostas.
Xiaoman LIU
Shenyang University of Technology
Yujie GAO
Shenyang University of Technology
Yuan HE
Shenyang University of Technology,Keio University
Xiaohan YUE
Shenyang University of Technology
Haiyan JIANG
Shenyang University of Technology
Xibo WANG
Shenyang University of Technology
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Xiaoman LIU, Yujie GAO, Yuan HE, Xiaohan YUE, Haiyan JIANG, Xibo WANG, "Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks" in IEICE TRANSACTIONS on Electronics,
vol. E106-C, no. 10, pp. 570-579, October 2023, doi: 10.1587/transele.2022CTP0005.
Abstract: The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.2022CTP0005/_p
Copiar
@ARTICLE{e106-c_10_570,
author={Xiaoman LIU, Yujie GAO, Yuan HE, Xiaohan YUE, Haiyan JIANG, Xibo WANG, },
journal={IEICE TRANSACTIONS on Electronics},
title={Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks},
year={2023},
volume={E106-C},
number={10},
pages={570-579},
abstract={The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.},
keywords={},
doi={10.1587/transele.2022CTP0005},
ISSN={1745-1353},
month={October},}
Copiar
TY - JOUR
TI - Hybrid, Asymmetric and Reconfigurable Input Unit Designs for Energy-Efficient On-Chip Networks
T2 - IEICE TRANSACTIONS on Electronics
SP - 570
EP - 579
AU - Xiaoman LIU
AU - Yujie GAO
AU - Yuan HE
AU - Xiaohan YUE
AU - Haiyan JIANG
AU - Xibo WANG
PY - 2023
DO - 10.1587/transele.2022CTP0005
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E106-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2023
AB - The complexity and scale of Networks-on-Chip (NoCs) are growing as more processing elements and memory devices are implemented on chips. However, under strict power budgets, it is also critical to lower the power consumption of NoCs for the sake of energy efficiency. In this paper, we therefore present three novel input unit designs for on-chip routers attempting to shrink their power consumption while still conserving the network performance. The key idea behind our designs is to organize buffers in the input units with characteristics of the network traffic in mind; as in our observations, only a small portion of the network traffic are long packets (composed of multiple flits), which means, it is fair to implement hybrid, asymmetric and reconfigurable buffers so that they are mainly targeting at short packets (only having a single flit), hence the smaller power consumption and area overhead. Evaluations show that our hybrid, asymmetric and reconfigurable input unit designs can achieve an average reduction of energy consumption per flit by 45%, 52.3% and 56.2% under 93.6% (for hybrid designs) and 66.3% (for asymmetric and reconfigurable designs) of the original router area, respectively. Meanwhile, we only observe minor degradation in network latency (ranging from 18.4% to 1.5%, on average) with our proposals.
ER -