The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo apresenta um algoritmo de seleção de bloco de porta, que pode sintetizar um extrator de parâmetros adequado da memória endereçável por conteúdo baseada em pré-computação (PB-CAM) para aumentar a eficiência energética para aplicações específicas, como sistemas embarcados, microprocessador e SOC, etc. Além disso, é proposto um novo projeto de célula CAM com linha de bits única. O projeto de célula CAM proposto requer apenas uma linha de bits de carga pesada e é construído apenas com oito transistores. Todo o projeto PB-CAM foi descrito em Spice com processo CMOS TSMC 0.35 µm duplo-poli quádruplo metal. Usamos o Synopsys Nanosim para estimar o consumo de energia. Com um tamanho CAM de 128 palavras por 32 bits, os resultados experimentais mostraram que nosso PB-CAM proposto reduz efetivamente 18.21% das operações de comparação no CAM e economiza 16.75% na redução de energia ao sintetizar um extrator de parâmetros adequado do PB-CAM comparado com a contagem de 1 PB-CAM. Isto implica que o nosso PB-CAM proposto é mais flexível e adaptável para aplicações específicas.
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Shanq-Jang RUAN, Jui-Yuan HSIEH, Chia-Han LEE, "Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1249-1257, October 2009, doi: 10.1587/transele.E92.C.1249.
Abstract: This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1249/_p
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@ARTICLE{e92-c_10_1249,
author={Shanq-Jang RUAN, Jui-Yuan HSIEH, Chia-Han LEE, },
journal={IEICE TRANSACTIONS on Electronics},
title={Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory},
year={2009},
volume={E92-C},
number={10},
pages={1249-1257},
abstract={This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.},
keywords={},
doi={10.1587/transele.E92.C.1249},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - Synthesis and Design of Parameter Extractors for Low-Power Pre-Computation-Based Content-Addressable Memory
T2 - IEICE TRANSACTIONS on Electronics
SP - 1249
EP - 1257
AU - Shanq-Jang RUAN
AU - Jui-Yuan HSIEH
AU - Chia-Han LEE
PY - 2009
DO - 10.1587/transele.E92.C.1249
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - This paper presents a gate-block selection algorithm, which can synthesize a proper parameter extractor of the pre-computation-based content-addressable memory (PB-CAM) to enhance power efficiency for specific applications such as embedded systems, microprocessor and SOC, etc. Furthermore, a novel CAM cell design with single bit-line is proposed. The proposed CAM cell design requires only one heavy loading bit-line and merely is constructed with eight transistors. The whole PB-CAM design was described in Spice with TSMC 0.35 µm double-poly quadruple-metal CMOS process. We used Synopsys Nanosim to estimate power consumption. With a 128 words by 32 bits CAM size, the experimental results showed that our proposed PB-CAM effectively reduces 18.21% of comparison operations in the CAM and saves 16.75% in power reduction by synthesizing a proper parameter extractor of the PB-CAM compared with the 1's count PB-CAM. This implies that our proposed PB-CAM is more flexible and adaptive for specific applications.
ER -