The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É proposta uma nova memória flash embarcada de 300 MHz para microcontroladores dual-core com uma arquitetura ROM compartilhada. Uma de suas características é uma operação de leitura de pipeline de três estágios, que permite um passo de acesso reduzido e, portanto, reduz a penalidade de desempenho devido a conflitos de acessos ROM compartilhados. Outro recurso é um amplificador de detecção altamente sensível que atinge uma operação eficiente de pipeline com latência de dois ciclos e passo de um ciclo como resultado de um tempo de detecção reduzido de 0.63 ns. A combinação da arquitetura de pipeline e dos amplificadores de detecção propostos reduz significativamente as penalidades de conflito de acesso com ROM compartilhada e melhora o desempenho dos microcontroladores RISC dual-core de 32 bits em 30%.
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Shinya KAJIYAMA, Masamichi FUJITO, Hideo KASAI, Makoto MIZUNO, Takanori YAMAGUCHI, Yutaka SHINAGAWA, "A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1258-1264, October 2009, doi: 10.1587/transele.E92.C.1258.
Abstract: A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1258/_p
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@ARTICLE{e92-c_10_1258,
author={Shinya KAJIYAMA, Masamichi FUJITO, Hideo KASAI, Makoto MIZUNO, Takanori YAMAGUCHI, Yutaka SHINAGAWA, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers},
year={2009},
volume={E92-C},
number={10},
pages={1258-1264},
abstract={A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.},
keywords={},
doi={10.1587/transele.E92.C.1258},
ISSN={1745-1353},
month={October},}
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TY - JOUR
TI - A 300 MHz Embedded Flash Memory with Pipeline Architecture and Offset-Free Sense Amplifiers for Dual-Core Automotive Microcontrollers
T2 - IEICE TRANSACTIONS on Electronics
SP - 1258
EP - 1264
AU - Shinya KAJIYAMA
AU - Masamichi FUJITO
AU - Hideo KASAI
AU - Makoto MIZUNO
AU - Takanori YAMAGUCHI
AU - Yutaka SHINAGAWA
PY - 2009
DO - 10.1587/transele.E92.C.1258
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - A novel 300 MHz embedded flash memory for dual-core microcontrollers with a shared ROM architecture is proposed. One of its features is a three-stage pipeline read operation, which enables reduced access pitch and therefore reduces performance penalty due to conflict of shared ROM accesses. Another feature is a highly sensitive sense amplifier that achieves efficient pipeline operation with two-cycle latency one-cycle pitch as a result of a shortened sense time of 0.63 ns. The combination of the pipeline architecture and proposed sense amplifiers significantly reduces access-conflict penalties with shared ROM and enhances performance of 32-bit RISC dual-core microcontrollers by 30%.
ER -