The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo descreve a arquitetura e implementações de um circuito de sintonia digital automática para um filtro passa-banda complexo (BPF) em um transceptor de baixo consumo de energia e baixo custo para aplicações como autenticação pessoal e sistemas de redes de sensores sem fio. A análise do projeto arquitetônico demonstra que um filtro RC ativo em uma arquitetura de baixo FI pode ser pelo menos 47.7% menor em área do que um filtro G convencional.m-C filtro; além disso, apresenta uma implementação simples de um circuito de sintonia associado. O princípio de sintonia simultânea da frequência central e da largura de banda através da calibração de um conjunto de capacitores é ilustrado com base em uma análise das características do filtro, e um circuito de sintonia digital automático escalável com blocos analógicos simples e lógica de controle com apenas 835 portas é introduzido. A técnica de sintonia de capacitores desenvolvida pode atingir um erro de sintonia inferior a
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Hideaki KONDO, Masaru SAWADA, Norio MURAKAMI, Shoichi MASUI, "Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 10, pp. 1304-1310, October 2009, doi: 10.1587/transele.E92.C.1304.
Abstract: This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.1304/_p
Copiar
@ARTICLE{e92-c_10_1304,
author={Hideaki KONDO, Masaru SAWADA, Norio MURAKAMI, Shoichi MASUI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers},
year={2009},
volume={E92-C},
number={10},
pages={1304-1310},
abstract={This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than
keywords={},
doi={10.1587/transele.E92.C.1304},
ISSN={1745-1353},
month={October},}
Copiar
TY - JOUR
TI - Design of Complex BPF with Automatic Digital Tuning Circuit for Low-IF Receivers
T2 - IEICE TRANSACTIONS on Electronics
SP - 1304
EP - 1310
AU - Hideaki KONDO
AU - Masaru SAWADA
AU - Norio MURAKAMI
AU - Shoichi MASUI
PY - 2009
DO - 10.1587/transele.E92.C.1304
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 10
JA - IEICE TRANSACTIONS on Electronics
Y1 - October 2009
AB - This paper describes the architecture and implementations of an automatic digital tuning circuit for a complex bandpass filter (BPF) in a low-power and low-cost transceiver for applications such as personal authentication and wireless sensor network systems. The architectural design analysis demonstrates that an active RC filter in a low-IF architecture can be at least 47.7% smaller in area than a conventional gm-C filter; in addition, it features a simple implementation of an associated tuning circuit. The principle of simultaneous tuning of both the center frequency and bandwidth through calibration of a capacitor array is illustrated as based on an analysis of filter characteristics, and a scalable automatic digital tuning circuit with simple analog blocks and control logic having only 835 gates is introduced. The developed capacitor tuning technique can achieve a tuning error of less than
ER -