The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Neste artigo, propomos novas portas AND baseadas em portas de transmissão (baseadas em TG), portas OR baseadas em TG e portas lógicas de transistor de passagem que possuem novas estruturas e têm contagens de transistores mais baixas do que aquelas propostas por outros autores. Todas as portas propostas operam em pleno andamento e têm menos correntes de fuga e atrasos mais curtos do que as portas CMOS convencionais. Em comparação com as portas CMOS convencionais de 65 nm, nossas portas de 65 nm propostas neste artigo podem melhorar as correntes de fuga, o consumo dinâmico de energia e os atrasos de propagação em médias de 42.4%, 8.1% e 13.5%, respectivamente. Os sintetizadores lógicos podem usá-los para facilitar a redução de potência. Os resultados experimentais mostram que uma ferramenta comercial de otimização de potência pode reduzir ainda mais a corrente de fuga e a potência dinâmica em até 39.85% e 18.69%, respectivamente, quando a biblioteca de células padrão usada pela ferramenta contém nossas portas propostas.
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Tsung-Yi WU, Liang-Ying LU, "Low-Leakage and Low-Power Implementation of High-Speed Logic Gates" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 401-408, April 2009, doi: 10.1587/transele.E92.C.401.
Abstract: In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.401/_p
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@ARTICLE{e92-c_4_401,
author={Tsung-Yi WU, Liang-Ying LU, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Leakage and Low-Power Implementation of High-Speed Logic Gates},
year={2009},
volume={E92-C},
number={4},
pages={401-408},
abstract={In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.},
keywords={},
doi={10.1587/transele.E92.C.401},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Low-Leakage and Low-Power Implementation of High-Speed Logic Gates
T2 - IEICE TRANSACTIONS on Electronics
SP - 401
EP - 408
AU - Tsung-Yi WU
AU - Liang-Ying LU
PY - 2009
DO - 10.1587/transele.E92.C.401
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents and shorter delays than conventional CMOS gates. Compared with the conventional 65 nm CMOS gates, our proposed 65 nm gates in this paper can improve leakage currents, dynamic power consumption, and propagation delays by averages of 42.4%, 8.1%, and 13.5%, respectively. Logic synthesizers can use them to facilitate power reduction. The experimental results show that a commercial power optimization tool can further reduce the leakage current and dynamic power up to 39.85% and 18.69%, respectively, when the standard cell library used by the tool contains our proposed gates.
ER -