The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um algoritmo de raiz quadrada (SR), uma arquitetura SR e um circuito de redução de corrente de fuga foram desenvolvidos para reduzir a potência dinâmica (PAT) e potência de fuga (PST), mantendo a velocidade de um circuito CMOS SR. Usando essas técnicas, um CMOS LSI de 90 nm foi fabricado. O PAT do novo circuito SR em uma frequência de clock (fc) de 490 MHz e uma tensão de alimentação (VDD) de 0.75 V foi de 104.1 µW, ou seja, 21.6% (482.3 µW) de um circuito SR convencional. O PST do novo circuito SR foi marcadamente reduzido para 19.51 nW, o que foi apenas 1.69% (1,153 nW) do circuito SR convencional.
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Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, "Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 409-416, April 2009, doi: 10.1587/transele.E92.C.409.
Abstract: A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.409/_p
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@ARTICLE{e92-c_4_409,
author={Tadayoshi ENOMOTO, Nobuaki KOBAYASHI, },
journal={IEICE TRANSACTIONS on Electronics},
title={Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit},
year={2009},
volume={E92-C},
number={4},
pages={409-416},
abstract={A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.},
keywords={},
doi={10.1587/transele.E92.C.409},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Low-Dynamic-Power and Low-Leakage-Power Techniques for CMOS Square-Root Circuit
T2 - IEICE TRANSACTIONS on Electronics
SP - 409
EP - 416
AU - Tadayoshi ENOMOTO
AU - Nobuaki KOBAYASHI
PY - 2009
DO - 10.1587/transele.E92.C.409
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - A square-root (SR) algorithm, an SR architecture and a leakage current reduction circuit were developed to reduce dynamic power (PAT) and leakage power (PST), while maintaining the speed of a CMOS SR circuit. Using these techniques, a 90-nm CMOS LSI was fabricated. The PAT of the new SR circuit at a clock frequency (fc) of 490 MHz and a supply voltage (VDD) of 0.75 V was 104.1 µW, i.e., 21.6% that (482.3 µW) of a conventional SR circuit. The PST of the new SR circuit was markedly reduced to 19.51 nW, which was only 1.69% that (1,153 nW) of the conventional SR circuit.
ER -