The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma nova SRAM confiável com células de memória 7T/14T e introduz um novo conceito, "qualidade de um bit (QoB)" para ela. A SRAM proposta tem três modos: um modo normal, um modo de alta velocidade e um modo confiável, e dimensiona dinamicamente sua confiabilidade, potência e velocidade combinando duas células de memória para informações de um bit (ou seja, 14 T/bit). Ao realizar a simulação de Monte Carlo em uma tecnologia de processo de 65 nm, as tensões mínimas nas operações de leitura e gravação são melhoradas em 0.21 V e 0.26 V, respectivamente, com uma taxa de erro de bit de 10-8 mantido. Além disso, confirmamos que o modo confiável atinge uma taxa de erro de bits menor do que o código de correção de erros (ECC) e a redundância multimódulo (MMR). Além disso, propomos uma nova estrutura de array de memória para evitar o problema de meia seleção em uma operação de escrita. Os respectivos overheads de área da célula no modo normal são de 26% e 11% nos casos em que os transistores adicionais são pMOSes e nMOSes, em comparação com a célula de memória 6T convencional.
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Hidehiro FUJIWARA, Shunsuke OKUMURA, Yusuke IGUCHI, Hiroki NOGUCHI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, "A Dependable SRAM with 7T/14T Memory Cells" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 423-432, April 2009, doi: 10.1587/transele.E92.C.423.
Abstract: This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14 T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21 V and 0.26 V, respectively, with a bit error rate of 10-8 kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.423/_p
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@ARTICLE{e92-c_4_423,
author={Hidehiro FUJIWARA, Shunsuke OKUMURA, Yusuke IGUCHI, Hiroki NOGUCHI, Hiroshi KAWAGUCHI, Masahiko YOSHIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Dependable SRAM with 7T/14T Memory Cells},
year={2009},
volume={E92-C},
number={4},
pages={423-432},
abstract={This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14 T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21 V and 0.26 V, respectively, with a bit error rate of 10-8 kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell.},
keywords={},
doi={10.1587/transele.E92.C.423},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - A Dependable SRAM with 7T/14T Memory Cells
T2 - IEICE TRANSACTIONS on Electronics
SP - 423
EP - 432
AU - Hidehiro FUJIWARA
AU - Shunsuke OKUMURA
AU - Yusuke IGUCHI
AU - Hiroki NOGUCHI
AU - Hiroshi KAWAGUCHI
AU - Masahiko YOSHIMOTO
PY - 2009
DO - 10.1587/transele.E92.C.423
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper proposes a novel dependable SRAM with 7T/14T memory cells, and introduces a new concept, "quality of a bit (QoB)" for it. The proposed SRAM has three modes: a normal mode, high-speed mode, and dependable mode, and dynamically scales its reliability, power and speed by combining two memory cells for one-bit information (i.e. 14 T/bit). By carrying out Monte Carlo simulation in a 65-nm process technology, the minimum voltages in read and write operations are improved by 0.21 V and 0.26 V, respectively, with a bit error rate of 10-8 kept. In addition, we confirm that the dependable mode achieves a lower bit error rate than the error correction code (ECC) and multi module redundancy (MMR). Furthermore, we propose a new memory array structure to avoid the half-selection problem in a write operation. The respective cell area overheads in the normal mode are 26% and 11% in the cases where additional transistors are pMOSes and nMOSes, compared to the conventional 6T memory cell.
ER -