The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Este artigo propõe uma arquitetura de cache de tamanho de linha variável controlável por software (SC-VLS) para sistemas embarcados de baixo consumo de energia. A alta largura de banda entre a lógica e uma DRAM é obtida por meio de tecnologia integrada avançada. System-in-Silicon é uma das estruturas arquitetônicas para obter alta largura de banda. Um ASIC e uma SRAM específica são montados em um intermediário de silício. Cada chip é conectado ao interpositor de silício por pontos de solda eutética. Neste contexto, é importante reduzir o consumo de energia DRAM. A DRAM específica precisa de uma pequena memória cache para melhorar o desempenho. Exploramos o cache para reduzir o consumo de energia DRAM. Durante as execuções do programa aplicativo, um tamanho de linha de cache adequado que produz a menor taxa de falta de cache é variado porque a quantidade de localidade espacial das referências de memória muda. Se empregarmos um tamanho de linha de cache grande, podemos esperar o efeito da pré-busca. No entanto, o consumo de energia DRAM é maior do que uma linha pequena devido ao grande número de bancos acessados. O cache SC-VLS é capaz de alterar o tamanho de uma linha para um tamanho adequado em tempo de execução com uma área pequena e sobrecarga de energia. Analisamos o tamanho de linha adequado e inserimos instruções de alteração de tamanho de linha no início de cada função de um programa alvo antes de executar o programa. Em nossa avaliação observa-se que o cache SC-VLS reduz o consumo de energia DRAM em até 88%, comparado a um cache convencional com linhas fixas de 256 B.
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Takatsugu ONO, Koji INOUE, Kazuaki MURAKAMI, Kenji YOSHIDA, "Reducing On-Chip DRAM Energy via Data Transfer Size Optimization" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 433-443, April 2009, doi: 10.1587/transele.E92.C.433.
Abstract: This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.433/_p
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@ARTICLE{e92-c_4_433,
author={Takatsugu ONO, Koji INOUE, Kazuaki MURAKAMI, Kenji YOSHIDA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Reducing On-Chip DRAM Energy via Data Transfer Size Optimization},
year={2009},
volume={E92-C},
number={4},
pages={433-443},
abstract={This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.},
keywords={},
doi={10.1587/transele.E92.C.433},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Reducing On-Chip DRAM Energy via Data Transfer Size Optimization
T2 - IEICE TRANSACTIONS on Electronics
SP - 433
EP - 443
AU - Takatsugu ONO
AU - Koji INOUE
AU - Kazuaki MURAKAMI
AU - Kenji YOSHIDA
PY - 2009
DO - 10.1587/transele.E92.C.433
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - This paper proposes a software-controllable variable line-size (SC-VLS) cache architecture for low power embedded systems. High bandwidth between logic and a DRAM is realized by means of advanced integrated technology. System-in-Silicon is one of the architectural frameworks to realize the high bandwidth. An ASIC and a specific SRAM are mounted onto a silicon interposer. Each chip is connected to the silicon interposer by eutectic solder bumps. In the framework, it is important to reduce the DRAM energy consumption. The specific DRAM needs a small cache memory to improve the performance. We exploit the cache to reduce the DRAM energy consumption. During application program executions, an adequate cache line size which produces the lowest cache miss ratio is varied because the amount of spatial locality of memory references changes. If we employ a large cache line size, we can expect the effect of prefetching. However, the DRAM energy consumption is larger than a small line size because of the huge number of banks are accessed. The SC-VLS cache is able to change a line size to an adequate one at runtime with a small area and power overheads. We analyze the adequate line size and insert line size change instructions at the beginning of each function of a target program before executing the program. In our evaluation, it is observed that the SC-VLS cache reduces the DRAM energy consumption up to 88%, compared to a conventional cache with fixed 256 B lines.
ER -