The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
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The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
As operações lógicas na integração digital CMOS são altamente propensas a falhar à medida que a quantidade de queda da fonte de alimentação (PS) se aproxima do limite de falha. A variação de tensão do PS é caracterizada por monitores de ruído embutidos em um microprocessador de 32 bits com tecnologia CMOS de 90 nm, e relacionada com falhas de operação por meio de programação em nível de instrução para análise lógica de falhas. A combinação do tamanho da queda de tensão e do caminho lógico ativado determina a sensibilidade à falha e a classe de falhas. A observação experimental, bem como a simulação simplificada, são aplicadas para a compreensão detalhada do impacto do ruído PS nas operações lógicas de circuitos integrados digitais.
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Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA, "Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 4, pp. 475-482, April 2009, doi: 10.1587/transele.E92.C.475.
Abstract: Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.475/_p
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@ARTICLE{e92-c_4_475,
author={Mitsuya FUKAZAWA, Masanori KURIMOTO, Rei AKIYAMA, Hidehiro TAKATA, Makoto NAGATA, },
journal={IEICE TRANSACTIONS on Electronics},
title={Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations},
year={2009},
volume={E92-C},
number={4},
pages={475-482},
abstract={Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.},
keywords={},
doi={10.1587/transele.E92.C.475},
ISSN={1745-1353},
month={April},}
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TY - JOUR
TI - Experimental Evaluation of Dynamic Power Supply Noise and Logical Failures in Microprocessor Operations
T2 - IEICE TRANSACTIONS on Electronics
SP - 475
EP - 482
AU - Mitsuya FUKAZAWA
AU - Masanori KURIMOTO
AU - Rei AKIYAMA
AU - Hidehiro TAKATA
AU - Makoto NAGATA
PY - 2009
DO - 10.1587/transele.E92.C.475
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2009
AB - Logical operations in CMOS digital integration are highly prone to fail as the amount of power supply (PS) drop approaches to failure threshold. PS voltage variation is characterized by built-in noise monitors in a 32-bit microprocessor of 90-nm CMOS technology, and related with operation failures by instruction-level programming for logical failure analysis. Combination of voltage drop size and activated logic path determines failure sensitivity and class of failures. Experimental observation as well as simplified simulation is applied for the detailed understanding of the impact of PS noise on logical operations of digital integrated circuits.
ER -