The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
Um loop de bloqueio de fase (PLL) de 60 GHz com um pré-escalador sem indutor é fabricado em um processo CMOS de 90 nm. O pré-escalador sem indutor possui uma área de chip menor do que os relatados anteriormente. O PLL opera de 61 a 63 GHz e consome 78 mW de uma fonte de 1.2 V. O ruído de fase em 100 kHz e deslocamento de 1 MHz da portadora é de -72 e -80 dBc/Hz, respectivamente. O prescaler ocupa 80
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Hiroaki HOSHINO, Ryoichi TACHIBANA, Toshiya MITOMO, Naoko ONO, Yoshiaki YOSHIHARA, Ryuichi FUJIMOTO, "A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 785-791, June 2009, doi: 10.1587/transele.E92.C.785.
Abstract: A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.785/_p
Copiar
@ARTICLE{e92-c_6_785,
author={Hiroaki HOSHINO, Ryoichi TACHIBANA, Toshiya MITOMO, Naoko ONO, Yoshiaki YOSHIHARA, Ryuichi FUJIMOTO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS},
year={2009},
volume={E92-C},
number={6},
pages={785-791},
abstract={A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80
keywords={},
doi={10.1587/transele.E92.C.785},
ISSN={1745-1353},
month={June},}
Copiar
TY - JOUR
TI - A 60-GHz Phase-Locked Loop with Inductor-Less Wide Operation Range Prescaler in 90-nm CMOS
T2 - IEICE TRANSACTIONS on Electronics
SP - 785
EP - 791
AU - Hiroaki HOSHINO
AU - Ryoichi TACHIBANA
AU - Toshiya MITOMO
AU - Naoko ONO
AU - Yoshiaki YOSHIHARA
AU - Ryuichi FUJIMOTO
PY - 2009
DO - 10.1587/transele.E92.C.785
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - A 60-GHz phase-locked loop (PLL) with an inductor-less prescaler is fabricated in a 90-nm CMOS process. The inductor-less prescaler has a smaller chip area than previously reported ones. The PLL operates from 61 to 63 GHz and consumes 78 mW from a 1.2 V supply. The phase noise at 100 kHz and 1 MHz offset from carrier are -72 and -80 dBc/Hz, respectively. The prescaler occupies 80
ER -