The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. ex. Some numerals are expressed as "XNUMX".
Copyrights notice
The original paper is in English. Non-English content has been machine-translated and may contain typographical errors or mistranslations. Copyrights notice
É desenvolvido um conversor analógico-digital (A/D) de largura de banda de entrada de 1 GHz para um receptor de rádio de impulso de banda ultralarga (UWB-IR). Tanto um circuito sample-and-hold (S/H) de subamostragem quanto um comparador dinâmico de redução de corrente são propostos para o conversor A/D. Um circuito S/H de subamostragem, que digitaliza um sinal de entrada em uma frequência mais alta do que a frequência de amostragem com baixo consumo de energia, é necessário porque o sistema UWB-IR utiliza impulsos ultracurtos intermitentes. O circuito S/H proposto executa a amostragem separando um capacitor de amostragem de um amplificador operacional e acumulando a tensão de deslocamento do amplificador no outro capacitor. O comparador de redução dinâmica de corrente proposto reduz a corrente de polarização dinamicamente correspondente ao seu nível de tensão de entrada. O conversor A/D é implementado em uma tecnologia de processo CMOS de 0.18 µm, que atinge um número efetivo de bits de 5.5, 5.4 e 4.9 para sinais de entrada com frequências de 1, 513 e 1057 MHz, respectivamente, em amostras de 32 M. /s. O conversor consome 0.89 mA e 0.42 mA na componente analógica e digital, respectivamente, na alimentação de 1.8 V.
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Copiar
Tatsuo NAKAGAWA, Tatsuji MATSUURA, Eiki IMAIZUMI, Junya KUDOH, Goichi ONO, Masayuki MIYAZAKI, "1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver" in IEICE TRANSACTIONS on Electronics,
vol. E92-C, no. 6, pp. 835-842, June 2009, doi: 10.1587/transele.E92.C.835.
Abstract: A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E92.C.835/_p
Copiar
@ARTICLE{e92-c_6_835,
author={Tatsuo NAKAGAWA, Tatsuji MATSUURA, Eiki IMAIZUMI, Junya KUDOH, Goichi ONO, Masayuki MIYAZAKI, },
journal={IEICE TRANSACTIONS on Electronics},
title={1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver},
year={2009},
volume={E92-C},
number={6},
pages={835-842},
abstract={A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.},
keywords={},
doi={10.1587/transele.E92.C.835},
ISSN={1745-1353},
month={June},}
Copiar
TY - JOUR
TI - 1-GHz Input Bandwidth Under-Sampling A/D Converter with Dynamic Current Reduction Comparator for UWB-IR Receiver
T2 - IEICE TRANSACTIONS on Electronics
SP - 835
EP - 842
AU - Tatsuo NAKAGAWA
AU - Tatsuji MATSUURA
AU - Eiki IMAIZUMI
AU - Junya KUDOH
AU - Goichi ONO
AU - Masayuki MIYAZAKI
PY - 2009
DO - 10.1587/transele.E92.C.835
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E92-C
IS - 6
JA - IEICE TRANSACTIONS on Electronics
Y1 - June 2009
AB - A 1-GHz input bandwidth analog-to-digital (A/D) converter for an ultra-wideband impulse radio (UWB-IR) receiver is developed. Both an under-sampling sample-and-hold (S/H) circuit and a dynamic current-reduction comparator are proposed for the A/D converter. An under-sampling S/H circuit, which digitizes an input signal at a higher frequency than the sampling frequency with low power consumption, is required because the UWB-IR system utilizes intermittent ultrashort impulses. The proposed S/H circuit executes sampling by separating a sampling capacitor from an operational amplifier and accumulating the offset voltage of the amplifier in the other capacitor. The proposed dynamic current reduction comparator reduces bias current dynamically corresponding to its input-voltage level. The A/D converter is implemented in a 0.18-µm CMOS process technology, which achieves an effective number of bits of 5.5, 5.4, and 4.9 for input signals with frequencies of 1, 513, and 1057 MHz, respectively, at 32 M samples/s. The converter consumes 0.89 mA and 0.42 mA in the analog and digital component, respectively, at a 1.8-V supply.
ER -